
Data Device Corporation
62743_pre2.DOC
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8-15-01
20
Table 15. Address Mapping
ADDRESS LINES
A4
A3
A2
A1
A0
REGISTER
DESCRIPTION / ACCESSIBILITY
0
1
0
1
Time Tag Register (RD/WR)
0
1
0
Interrupt Status Register #1(RD)
0
1
Configuration Register #3 (RD/WR)
0
1
0
Configuration Register #4 (RD/WR)
0
1
0
1
Configuration Register #5 (RD/WR)
0
1
0
1
0
RT/Monitor Data Stack Address Register (RD/WR)
0
1
0
1
BC Frame Time Remaining Register (RD)
0
1
0
BC Time Remaining to Next Message Register (RD)
0
1
0
1
Non-Enhanced BC Frame Time/Enhanced BC Initial Instruction
Pointer /RT Last Command/MT Trigger Word Register (RD/WR)
0
1
0
RT Status Word Register (RD)
0
1
RT BIT Word Register (RD)
1
0
Test Mode Register 0
1
0
1
Test Mode Register 1
1
0
1
0
Test Mode Register 2
1
0
1
Test Mode Register 3
1
0
1
0
Test Mode Register 4
1
0
1
0
1
Test Mode Register 5
1
0
1
0
Test Mode Register 6
1
0
1
Test Mode Register 7
1
0
Configuration Register #6 (RD/WR)
1
0
1
Configuration Register #7 (RD/WR)
1
0
1
0
RESERVED
1
0
1
BC Condition Code Register (RD)
1
0
1
BC General Purpose Flag Register (WR)
1
0
RESERVED
1
0
1
Interrupt Mask Register #2 (RD/WR)
1
0
Interrupt Status Register #2 (RD)
1
BC General Purpose Queue Pointer/
RT-MT Interrupt Status Queue Pointer Register (RD/WR)