
Data Device Corporation
62743_pre2.DOC
www.ddc-web.com
8-15-01
11
The receiver sections of the PCI Enhanced Mini-ACE are fully compliant with
MIL-STD-1553B Notice 2 in terms of front-end overvoltage protection, threshold,
common mode rejection, and word error rate.
PCI REGISTER AND MEMORY ADDRESSING
The PCI Interface contains a set of “Type 00h” PCI configuration registers that
are used to map the device into the host system. The PCI configuration register
space is mapped in accordance with PCI revision 2.2 specifications.
Table 2. Configuration Register Space for the P-prime ASIC
Address
31
24
23
16
15
8
7
0
Device ID
Vendor ID
00h
04h
00h (1553 terminal
mode)
01h (Bolt On PCI
mode)
DDC Manufacturer Device ID value (4DDC
H)
04h
Status Register
Command Register
08h
Class Code = 078000 h
Rev ID = 01
0Ch
BIST (not
implemented)
Header Type
00h
Latency Timer
Cache Line Size
Base Address Register 0 (for ACE memory)
10h
R/W
R/W and 0's
see text
00h
04h
Base Address Register 1 (for ACE registers)
14h
R/W
R/W and 0's
see text
04h
18h
Base Address Register 2 (for local RAM) 128K byte window
1Ch - 24h
Base Address Registers 3 through 5 (not used) 00000000h
28h
Card Bus CIS pointer (not used) 00000000h
2Ch
Subsystem Device and Subsystem Vendor ID Same as Configuration Register 0, Alias
Reads to Configuration Register 00 (1553 terminal mode)
User configurable (Bolt On PCI interface mode) - see text.
30h
Expansion ROM Base Address (Not Used, bit 0 = 0)
34h-38h
Reserved
3Ch
Max Lat.
00h
Min Gnt
00h
Interrupt Pin
01h
Interrupt Line
R/W
This data sheet will only describe the PCI registers that are specific to
configuring the integrated terminal, and shared RAM. For specifics or definitions
on other PCI bus configuration registers, please see the PCI Local Bus
specification revision 2.2.
Vendor ID field contains the vendor’s ID configuration register. Data Device
Corporation’s ID code is 4DDCh.