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參數(shù)資料
| 型號： | BU-62843B3-120L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
| 封裝： | 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, 1 MM PITCH, BGA-128 |
| 文件頁數(shù)： | 25/93頁 |
| 文件大小： | 504K |
| 代理商： | BU-62843B3-120L |
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Data Device Corporation
62743_pre2.DOC.doc
www.ddc-web.com
8-15-01
31
used for minor or major frame control, or as a watchdog timer for the BC
message sequence control processor. The resolution of this register is 100
s/LSB.
BC Time Remaining to Next Message Register provides a read-only indication
of the time remaining before the start of the next message in a BC frame. In the
enhanced BC mode, this timer may be also be used for the BC message
sequence control processor’s Delay (DLY) instruction, or for minor or major
frame control. The resolution of this register is 1
s/LSB.
BC Frame Time/RT Last Command/MT Trigger Word Register. In BC mode,
this register is used to program the BC frame time, for use in the frame auto-
repeat mode. The resolution of this register is 100
s/LSB, with a range up to
6.55 seconds. In RT mode, this register stores the current (or most previous)
1553 Command Word processed by the PCI Enhanced Mini-ACE RT. In the
Word Monitor mode, this register is used to specify a 16-bit Trigger (Command)
Word.
The Trigger Word may be used to start or stop the monitor, or to
generate interrupts.
BC Initial Instruction List Pointer Register enables the host to assign the
starting address for the enhanced BC Instruction List.
RT Status Word Register and BIT Word Registers provide read-only
indications of the RT Status and BIT Words.
Test Mode Registers 0-7.
These registers are included for factory test. In
normal operation, these registers do not need to be accessed by the host
processor.
Configuration Registers #6 and #7 are used to enable the PCI Enhanced Mini-
ACE features that extend beyond the architecture of the ACE/Mini-ACE (Plus).
These includes the Enhanced BC mode; RT Global Circular Buffer (including
buffer size); the RT/MT Interrupt Status Queue, including valid/invalid message
filtering; enabling a software-assigned RT address; clock frequency selection; a
base address for the “non-data” portion of PCI Enhanced Mini-ACE memory;
LSB filtering for the Synchronize (with data) time tag operations; and enabling a
watchdog timer for the Enhanced BC message sequence control engine.
BC Condition Code Register is used to enable the host processor to read the
current value of the Enhanced BC Message Sequence Control Engine’s
condition flags.
BC General Purpose Flag Register allows the host processor to be able to set,
clear, or toggle any of the Enhanced BC Message Sequence Control Engine’s
General Purpose condition flags.
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