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參數(shù)資料
| 型號(hào)： | BU-62743G3-400Y |
| 廠商： | DATA DEVICE CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 INCH, CERAMIC, QFP-72 |
| 文件頁(yè)數(shù)： | 92/99頁(yè) |
| 文件大小： | 578K |
| 代理商： | BU-62743G3-400Y |
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Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
92
Table 72. SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS
PCI BUS CONTROL SIGNALS
(Note that all signals listed, except INTA#, are sampled on the rising edge of PCI_CLK)
SIGNAL
NAME
PIN (F & G
Package)
DESCRIPTION
FRAME#
(I)
44
Frame. This signal is driven by the current bus master and identifies both the
beginning and duration of a bus operation.
When FRAME# is first asserted, it
indicates that a bus transaction is beginning and that valid addresses and a
corresponding bus command are present on the AD[31:0] and C/BE[3:0] lines,
qualified by PCI _CLK. When FRAME# is deasserted the transaction is in the
final data phase or has been completed.
IRDY# (I)
45
Initiator Ready. This signal is sourced by the bus master and indicates that the
bus master is able to complete the current data phase of a bus transaction. For
write operations, it indicates that valid data is on the AD[31:0] pins. Wait states
occur until both TRDY# and IRDY# are asserted together.
TRDY# (O)
46
Target Ready. This signal is sourced by the selected target and indicates that
the target is able to complete the current data phase of a bus transaction. For
read operations, it indicates that the target is providing valid data on the
AD[31:0] pins.
Wait states occur until both TRDY# and IRDY# are asserted
together.
STOP# (O)
48
Stop. The Stop signal is sourced by the selected target and conveys a request
to the bus master to stop the current transaction.
IDSEL (I)
33
Initialization Device Select. This pin is used as a chip select during configuration
read or write operations.
DEVSEL#
(O)
47
Device Select. This signal is sourced by an active target upon decoding that its
address and bus commands are valid. For bus masters, it indicates whether
any device has decoded the current bus cycle.
PERR# (O)
49
Parity Error. This pin is used for reporting parity errors during the data portion of
the bus transaction for all cycles except a Special Cycle. It is sourced by the
agent receiving data and driven active two clocks following the detection of an
error. This signal is driven inactive (high) two clocks prior to returning to the tri-
state condition.
SERR# (O)
50
System Error. This pin is used for reporting address parity errors, data parity
errors on Special Cycle commands, or any other condition having a catastrophic
system impact.
INTA# (O)
21
Interrupt A. This pin is a level sensitive, active low interrupt to the host.
FACTORY TEST
SIGNAL
PIN
(F & G Package)
DESCRIPTION
XCVR_TP (ZAP VOLTA)
P1(*)
XCVR_TP (READOUTB)
P2(*)
XCVR_TP (READOUTA)
P3(*)
XCVR_TP (CLOCK)
P4(*)
XCVR_TP (RESET*)
P5(*)
XCVR_TP (ZAP VOLTB)
P6(*)
For factory test only. Do not connect for normal
operation.
(*) Note that the Test Output pins are pads located on the package bottom.
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