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參數(shù)資料
| 型號： | BU-62743G3-142L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 INCH, CERAMIC, QFP-72 |
| 文件頁數(shù)： | 36/99頁 |
| 文件大小： | 578K |
| 代理商： | BU-62743G3-142L |
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Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
41
purpose flag bits, or an immediate value. For several op codes, the parameter is
“don’t care” (not used).
As described above, some of the op codes will cause the message sequence
control processor to execute messages. In this case, the parameter references the
first word of a message control/status block. With the exception of RT-to-RT
transfer messages, all message status/control blocks are eight words long: a block
control word, time-to-next-message parameter, data block pointer, command word,
status word, loopback word, block status word, and time tag word.
In the case of an RT-to-RT transfer message, the size of the message
control/status block increases to 16 words. However, in this case, the last six
words are not used; the ninth and tenth words are for the second command word
and second status word.
The third word in the message control/status block is a pointer that references the
first word of the message’s data word block. Note that the data word block stores
only data words, which are to be either transmitted or received by the BC. By
segregating data words from command words, status words, and other control and
“housekeeping” functions, this architecture enables the use of convenient, usable
data structures, such as circular buffers and double buffers.
Other operations support program flow control; i.e., jump and call capability. The
call capability includes maintenance of a call stack which supports a maximum of
four (4) entries; there is also a return instruction. In the case of a call stack overrun
or underrun, the BC will issue an CALL STACK POINTER REGISTER ERROR
interrupt, if enabled.
Other op codes may be used to delay for a specified time; start a new BC frame;
wait for an external trigger to start a new frame; do comparisons based on frame
time and time-to-next message; load the time tag or frame time registers; halt; and
issue host interrupts. In the case of host interrupts, the message control processor
passes a 4-bit user-defined interrupt vector to the host, by means of the PCI
Enhanced Mini-ACE’s Interrupt Status Register.
The purpose of the FLG instruction is to enable the message sequence controller
to set, clear, or toggle the value(s) of any or all of the eight general purpose
condition flags.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Odd
Parity
OpCode Field
0
1
0
1
0
Condition Code Field
Figure 3. BC Op Code Format
相關(guān)PDF資料 |
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| BU-62743G3-142Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62743G3-142Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62743G3-152K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62743G3-152 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62743G3-160Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
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