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    參數(shù)資料
    型號(hào): BU-62743F4-300S
    廠商: DATA DEVICE CORP
    元件分類: 微控制器/微處理器
    英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
    封裝: 1 INCH, CERAMIC, QFP-72
    文件頁(yè)數(shù): 41/99頁(yè)
    文件大?。?/td> 578K
    代理商: BU-62743F4-300S
    Data Device Corporation
    62743_pre7_noSA-DB.DOC
    www.ddc-web.com
    8-07-02
    46
    Table 53. Condition Codes
    BIT
    CODE
    NAME
    (Bit 4 = 0)
    INVERSE
    (Bit 4 = 1)
    FUNCTIONAL DESCRIPTION
    0
    LT/GP0
    GT/GP0*
    Less Than Flag set or cleared after CFT or CMT operation. Also, General
    Purpose Flag 0 may be set or cleared by a FLG operation.
    1
    EQ/GP1
    NE/GP1*
    Equal Flag set or cleared after CFT or CMT operation. Also, General
    Purpose Flag 1 may be also be set or cleared by a FLG operation.
    2
    GP2
    GP2*
    General Purpose Flags set or cleared by FLG operation or by host
    processor. The host processor can set, clear, or toggle these flags in the
    same way as the FLG instruction by means of the BC GENERAL
    PURPOSE FLAG REGISTER.
    3
    GP3
    GP3*
    4
    GP4
    GP4*
    5
    GP5
    GP5*
    6
    GP6
    GP6*
    7
    GP7
    GP7*
    8
    NORESP
    RESP*
    NORESP indicates that an RT has either not responded or has responded
    later than the BC No Response Timeout time. The PCI Enhanced Mini-
    ACE's No Response Timeout Time is defined per MIL-STD-1553B as the
    time from the mid-bit crossing of the parity bit to the mid-sync crossing of
    the RT Status Word. The value of the No Response Timeout value is
    programmable from among the nominal values 18.5, 22.5, 50.5, and 130
    s (±1 s) by means of bits 10 and 9 of Configuration Register #5.
    9
    FMT ERR
    FMT ERR*
    FMT ERR indicates that the received portion of the most recent message
    contained one or more violations of the 1553 message validation criteria
    (sync, encoding, parity, bit count, word count, etc.), or the RT's status word
    received from a responding RT contained an incorrect RT address field.
    A
    GD BLK
    XFER
    GD BLK
    XFER*
    For the most recent message, GD BLK XFER will be set to logic "1"
    following completion of a valid (error-free) RT-to-BC transfer, RT-to-RT
    transfer, or transmit mode code with data message. This bit is set to logic
    "0" following an invalid message. GOOD DATA BLOCK TRANSFER is
    always logic "0" following a BC-to-RT transfer, a mode code with data, or a
    mode code without data. The Loop Test has no effect on GOOD DATA
    BLOCK TRANSFER. GOOD DATA BLOCK TRANSFER may be used to
    determine if the transmitting portion of an RT-to-RT transfer was error free.
    B
    MASKED
    STATUS
    SET
    MASKED
    STATUS
    BIT*
    Indicates that one or both of the following conditions have occurred for the
    most recent message: (1) If one (or more) of the Status Mask bits (14
    through 9) in the BC Control Word is logic "0" and the corresponding bit(s)
    is (are) set (logic "1") in the received RT Status Word. In the case of the
    RESERVED BITS MASK (bit 9) set to logic "0," any or all of the 3
    Reserved Status bits being set will result in a MASKED STATUS SET
    condition; and/or (2) If BROADCAST MASK ENABLED/XOR* (bit 11 of
    Configuration Register #4) is logic "1" and the MASK BROADCAST bit of
    the message's BC Control Word is logic "0" and the BROADCAST
    COMMAND RECEIVED bit in the received RT Status Word is logic "1.".
    C
    BAD
    MESSAGE
    GOOD
    MESSAGE
    BAD MESSAGE indicates either a format error, loop test fail, or no
    response error for the most recent message. Note that a “Status Set”
    condition has no effect on the “BAD MESSAGE/GOOD MESSAGE”
    condition code.
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