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Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
48
BC MESSAGE SEQUENCE CONTROL
The PCI Enhanced Mini-ACE BC message sequence control capability enables a
high degree of offloading of the host processor. This includes using the various
timing functions to enable autonomous structuring of major and minor frames. In
addition, by implementing conditional jumps and subroutine calls, the message
sequence control processor greatly simplifies the insertion of asynchronous, or
“out-of-band” messages.
Execute and Flip Operation. The PCI Enhanced Mini-ACE BC’s XQF, or
“Execute and Flip” operation, provides some unique capabilities. Following
execution of this unconditional instruction, if the condition code tests TRUE, the
BC will modify the value of the current XQF instruction’s pointer parameter by
toggling bit 4 in the pointer. That is, if the selected condition flag tests true, the
value of the parameter will be updated to the value = old address XOR 0010h.
As a result, the next time that this line in the instruction list is executed, the
Message Control/Status Block at the updated address (old address XOR 0010h),
will be processed, rather than the one at the old address,. The operation of the
XQF instruction is illustrated in Figure 4.
There are multiple ways of utilizing the “execute and flip” functionality. One is to
facilitate the implementation of a double buffering data scheme for individual
messages. This allows the message sequence control processor to “ping-pong”
between a pair of data buffers for a particular message. By so doing, the host
processor can access one of the two Data Word blocks, while the BC reads or
writes the alternate Data Word block.
A second application of the “execute and flip” capability is in association with
message retries. This allows the BC to not only switch buses when retrying a failed
message, but to automatically switch buses permanently for all future times that
the same message is to be processed. This not only provides a high degree of
autonomy from the host CPU, but saves BC bandwidth, by eliminating future
attempts to process messages on an RT’s failed channel.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-62743F3-440K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62743F3-440S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62743F3-440Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62743F3-440 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-62743F3-442L | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU-62843 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
| BU-62864 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
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