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參數(shù)資料
| 型號： | BU-62743F3-402 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 INCH, CERAMIC, QFP-72 |
| 文件頁數(shù)： | 91/99頁 |
| 文件大小： | 578K |
| 代理商： | BU-62743F3-402 |
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Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
91
Table 71. SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS
PCI BUS ADDRESS AND DATA SIGNALS
SIGNAL NAME
PIN (F & G
Package)
DESCRIPTION
C/BE[3]# (I)
32
C/BE[2]# (I)
43
C/BE[1]# (I)
52
C/BE[0]# (I)
61
Bus Command and Byte Enables. These signals are multiplexed on the same
pins. During the address phase of a bus operation, these pins identify the bus
command, as shown in the table below. During the data phase of a bus
operation, these pins are used as Byte Enables, with C/BE[0]# enabling byte 0
(LSB) and C/BE[3]# enabling byte 3 (MSB). The PACE responds to the
following PCI commands
C/BE[3:0]#
Description (during address phase)
0
1
0
Memory Read
0
1
Memory Write
1
0
1
0
Configuration Read
1
0
1
Configuration Write
1
0
Memory Read Multiple
1
0
Memory Read Line
1
Memory Write and Invalidate
Note that the last three memory commands are aliased to the basic memory
commands: Memory Read and Memory Write
PAR (I/O)
51
Parity. This signal is even parity across the entire AD[31:0] field along with the
C/BE[3:0]# field. The parity is stable in the clock following the address phase
and is sourced by the Bus Master. During the data phase for write operations,
the Bus Master sources this signal on the clock following IRDY# active.
During the data phase for read operations, this signal is sourced by the Target
and is valid on the clock following TRDY# active. The PAR signal therefore
has the same timing as AD[31:0], delayed by one clock.
PCI_CLK (I)
30
Clock input. The rising edge of this signal is the reference upon which all
other clock signals are based, with the exception of RST# and INTA#. The
maximum frequency accepted is 33 MHz and the minimum is 0 Hz.
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