<pre id="rz4fk"></pre>
  • <big id="rz4fk"><strong id="rz4fk"></strong></big>
    <big id="rz4fk"><xmp id="rz4fk">
  • <big id="rz4fk"><dfn id="rz4fk"><table id="rz4fk"></table></dfn></big>
  • 參數(shù)資料
    型號: BU-61865G4-192Y
    廠商: DATA DEVICE CORP
    元件分類: 微控制器/微處理器
    英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72
    封裝: GULL WING, PACKAGE-72
    文件頁數(shù): 30/56頁
    文件大?。?/td> 321K
    代理商: BU-61865G4-192Y
    36
    CLOCK IN
    VALID
    t7
    t3
    t8
    t11
    t13
    t15
    VALID
    t10
    t4
    t9
    t12
    t19
    ;
    ;;
    VALID
    t16
    t17
    SELECT
    (Note 2,7)
    (Note 2)
    (Note 3,4,7)
    (Note 4,5)
    STRBD
    MEM/REG
    RD/WR
    IOEN
    (Note 2,6)
    (Note 6)
    (Note 7,8,9)
    READYD
    A15-A0
    D15-D0
    ;
    ;;
    ;;;
    ;;
    t5
    t1
    t2
    t6
    t14
    t18
    FIGURE 13. CPU READING RAM / REGISTER (16-BIT BUFFERED, NONZERO WAIT)
    NOTES:
    1.
    For the 16-bit buffered nonzero wait configuration,
    must be connected to logic "0".
    and
    must be connected to logic "1". The inputs TRIGGER_SEL and MSB/LSB may be connected to either +5V or ground.
    2.
    and
    may be tied together.
    goes low on the first rising CLK edge when
    is sampled low (satisfying t1)
    and the Enhanced Mini-ACE's protocol/memory management logic is not accessing the internal RAM. When this occurs,
    goes low, start-
    ing the transfer cycle. After
    goes low,
    may be released high.
    3.
    must be presented high for memory access, low for register access.
    4.
    and
    are buffered transparently until the first falling edge of CLK after
    goes low. After this CLK edge,
    and
    become latched internally.
    5.
    The logic sense for
    in the diagram assumes that POLARITY_SEL is connected to logic "1." If POLARITY_SEL is connected to logic "0,"
    must be asserted low to read.
    6.
    The timing for
    ,
    and D15-D0 assumes a 50 pf load. For loading above 50 pf, the validity of
    ,
    , and D15-D0 is
    delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
    7.
    The timing for A15-A0,
    and
    assumes that ADDR-LAT is connected to logic "1." Refer to Address Latch timing for additional
    details.
    8.
    The address bus A15-A0 is internally buffered transparently until the first rising edge of CLK after
    goes low. After this CLK edge, A15-A0
    become latched internally.
    9.
    Setup time given for use in worst case timing calculations. None of the Enhanced Mini-ACE input signals are required to be synchronized to the
    system clock. When
    and
    do not meet the setup time of t1, but occur during the setup window of an internal flip-flop, an addi-
    tional clock cycle will be inserted between the falling clock edge that latches
    and
    and the rising clock edge that latches the
    Address (A15-A0). When this occurs, the delay from
    falling to
    falling (t11) increases by one clock cycle and the address hold
    time (t10) must be increased be one clock cycle.
    READYD
    IOEN
    WR
    /
    RD
    REG
    /
    MEM
    STRBD
    SELECT
    IOEN
    SELECT
    REG
    /
    MEM
    READYD
    IOEN
    READYD
    IOEN
    WR
    /
    RD
    WR
    /
    RD
    WR
    /
    RD
    REG
    /
    MEM
    IOEN
    WR
    /
    RD
    REG
    /
    MEM
    REG
    /
    MEM
    SELECT
    IOEN
    STRBD
    SELECT
    IOEN
    STRBD
    SELECT
    8
    /
    16
    /
    DTREQ
    WAIT
    ZERO
    BUFFERED
    /
    T
    TRANSPAREN
    相關(guān)PDF資料
    PDF描述
    BU-61743F4-132Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
    BU-61743F4-142Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
    BU-61743F4-192Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
    BU-61745F4-142Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
    BU-61745F4-172Z 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    BU-61XXX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MINIATURE ADVANCED COMMUNICATION ENGINE (MINI-ACE) AND MINI-ACE PLUS
    BU-62-0 功能描述:測試電夾 INSULATOR FOR 60 SERIES BLACK RoHS:否 制造商:Pomona Electronics 類型:Minigrabber clip 顏色:Black
    BU-62-2 功能描述:測試電夾 INSULATOR FOR 60 SERIES RED RoHS:否 制造商:Pomona Electronics 類型:Minigrabber clip 顏色:Black
    BU-62-4 功能描述:測試電夾 INSULATOR FOR 60 SERIES YELLOW RoHS:否 制造商:Pomona Electronics 類型:Minigrabber clip 顏色:Black
    BU-62-5 功能描述:測試電夾 INSULATOR FOR 60 SERIES GREEN RoHS:否 制造商:Pomona Electronics 類型:Minigrabber clip 顏色:Black