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參數(shù)資料
| 型號： | BU-61865F4-760Z |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 X 1 INCH, 0.155 INCH HEIGHT, CERAMIC, FP-72 |
| 文件頁數(shù)： | 43/60頁 |
| 文件大?。?/td> | 700K |
| 代理商： | BU-61865F4-760Z |
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48
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
Rev. C
TRANSPARENT /
BUFFERED
55
Used to select between the buffered mode (when strapped to logic “0”) and transparent/DMA mode (when
strapped to logic “1") for the host processor interface.
IOEN(O)
58
I/O Enable. Tri-state control for external address and data buffers. Generally not used in buffered mode.
When low, indicates that the Enhanced Mini-ACE is currently performing a host access to an internal reg-
ister, or internal or (for transparent mode) external RAM. In transparent mode, IOEN (low) should be used
to enable external address and data bus tri-state buffers.
READYD
56
Handshake output to host processor. For a nonzero wait state read access, READYD is asserted at the
end of a host transfer cycle to indicate that data is available to be read on D15 through D0 when asserted
(low). For a nonzero wait state write cycle, READYD is asserted at the end of the cycle to indicate that
data has been transferred to a register or RAM location. For both nonzero wait reads and writes, the host
must assert STRBD low until READYD is asserted low.
In the (buffered) zero wait state mode, this output is normally logic "1", indicating that the Enhanced Mini-ACE is
in a state ready to accept a subsequent host transfer cycle. In zero wait mode, READYD will transition from high
to low during (or just after) a host transfer cycle, when the Enhanced Mini-ACE initiates its internal transfer to or
from registers or internal RAM. When the Enhanced Mini-ACE completes its internal transfer, READYD returns
to logic "1", indicating it is ready for the host to initiate a subsequent transfer cycle.
RTAD4 (MSB) (I)
35
RT Address inputs. If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is programmed to logic
"0" (default), then the Enhanced Mini-ACE's RT address is provided by means of these 5 input signals. In
addition, if RT ADDRESS SOURCE is logic "0", the source of RT address parity is RTADP.
There are many methods for using these input signals for designating the Enhanced Mini-ACE's RT
address. For details, refer to the description of RT_AD_LAT.
If RT ADDRESS SOURCE is programmed to logic "1", then the Enhanced Mini-ACE's source for its RT
address and parity is under software control, via data lines D5-D0. In this case, the RTAD4-RTAD0 and
RTADP signals are not used.
RTAD3 (I)
34
RTAD2 (I)
21
RTAD1 (I)
41
RTAD0 (LSB) (I)
33
RT_AD_LAT (I)
31
RT Address Latch. Input signal used to control the Enhanced MINI-ACE's internal RT address latch. If
RT_AD_LAT is connected to logic "0", then the Enhanced Mini-ACE RT is configured to accept a hardwired
(transparent) RT address from RTAD4-RTAD) and RTADP.
If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values presented on RTAD4-RTAD0 and
RTADP will be latched internally on the rising edge of RT_AD_LAT.
If RT_AD_LAT is connected to logic "1", then the Enhanced Mini-ACE's RT address is latchable under host
processor control. In this case, there are two possibilities: (1) If bit 5 of Configuration Register #6, RT ADDRESS
SOURCE, is programmed to logic "0" (default), then the source of the RT Address is the RTAD4-RTAD0 and
RTADP input signals; (2) If RT ADDRESS SOURCE is programmed to logic "1", then the source of the RT
Address is the lower 6 bits of the processor data bus, D5-D1 (for RTAD4-0) and D0 (for RTADP).
In either of these two cases (with RT_AD_LAT = "1"), the processor will cause the RT address to be latched by: (1)
writing bit 15 of Configuration Register #3, ENHANCED MODE, to logic "1"; (2) writing bit 3 of Configuration
Register #4, LATCH RT ADDRESS WITH CONFIGURATION REGISTER #5, to logic "1"; and (3) writing to
Configuration Register #5. In the case of RT ADDRESS SOURCE = "1", then the values of RT address and RT
address parity must be written to the lower 6 bits of Configuration Register #5, via D5-D0. In the case where RT
ADDRESS SOURCE = "0", the bit values presented on D5-D0 become "don't care" .
RTADP
40
Remote Terminal Address Parity. This input signal must provide an odd parity sum with RTAD4-RTAD0 in
order for the RT to respond to non-broadcast commands. That is, there must be an odd number of logic
"1"s from among RTAD-4-RTAD0 and RTADP.
TABLE 51. PROCESSOR INTERFACE CONTROL (CONT.)
SIGNAL NAME
DESCRIPTION
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
PIN
TABLE 52. RT ADDRESS
SIGNAL NAME
DESCRIPTION
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
PIN
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