- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄255865 > BU-61865F4-502 (DATA DEVICE CORP) 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CQFP72 PDF資料下載
參數(shù)資料
| 型號(hào)： | BU-61865F4-502 |
| 廠商： | DATA DEVICE CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 X 1 INCH, 0.155 INCH HEIGHT, FP-72 |
| 文件頁(yè)數(shù)： | 43/56頁(yè) |
| 文件大?。?/td> | 304K |
| 代理商： | BU-61865F4-502 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)當(dāng)前第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)
48
60
59
2
30
25
60
59
2
30
25
TX_INH_B (1)
TX_INH_A (1)
MSTCLR(1)
CLOCK_IN (1)
INCMD (O) /
MCRST (O)
INT (0)
UPADDREN
Transmitter inhibit inputs for the Channel A and Channel B MIL-STD-1553 transmitters.
For normal operation, these inputs should be connected to logic "0". To force a shutdown
of Channel A and/or Channel B, a value of logic "1" should be applied to the respective
TX_INH input.
Master Clear. Negative true Reset input, normally asserted low following power turn-on.
When coming out of a “reset” condition, please note that the rise time of MSTCLR must
be less than 10 S.
20 MHz, 16 MHz, 12 MHz, or 10 MHz clock input.
In-command or Mode Code Reset. The function of this pin is controlled by bit 0 of
Configuration Register #7, MODE CODE RESET/INCMD SELECT.
If this register bit is logic "0" (default), INCMD will be active on this pin. For BC, RT, or
Selective Message Monitor modes, INCMD is asserted low whenever a message is being
processed by the Enhanced Mini-ACE. In Word Monitor mode, INCMD will be asserted
low for as long as the monitor is online.
For RT mode, if MODE CODE RESET/INCMD SELECT is programmed to logic "1",
MCRST will be active. In this case, MCRST will be asserted low for two clock cycles fol-
lowing receipt of a Reset remote terminal mode command.
In BC or Monitor modes, if MODE CODE RESET/INCMD SELECT is logic "1", this signal
is inoperative; i.e., in this case, it will always output a value of logic "1".
Interrupt Request output. If the LEVEL/PULSE interrupt bit (bit 3) of Configuration
Register #2 is logic "0", a negative pulse of approximately 500ns in width is output on
INT to signal an interrupt request.
If LEVEL/PULSE is high, a low level interrupt request output will be asserted on INT. The
level interrupt will be cleared (high) after either: (1) The processor writes a value of logic
"1" to INTERRUPT RESET, bit 2 of the Start/Reset Register; or (2) If bit 4 of
Configuration Register #2, INTERRUPT STATUS AUTO-CLEAR is logic "1", then it will
only be necessary to read the Interrupt Status Register (#1 and/or #2) that is requesting
an interrupt that has been enabled by the corresponding Interrupt Mask Register.
However, for the case where both Interrupt Status Register #1 and Interrupt Status
Register #2 have bits set reflecting interrupt events, it will be necessary to read both
interrupt status registers in order to clear INT.
For BU-61864/61865, this pin is +5V-RAM and MUST be connected to +5V.
For BU-61743(5) and 61843(5), this signal is used to control the function of the upper 4
address inputs (A15-A12). For these versions of Enhanced Mini-ACE, if UPADDREN is
connected to logic "1", then these four signals operate as address lines A15-A12.
For BU-61843(5)/61743(5), if UPADDREN is connected to logic "0", then A15 and A14
function as CLK_SEL_1 and CLK_SEL_0 respectively; A13 MUST be connected to Vcc-
LOGIC (+5V or +3.3V); and A12 functions as RTBOOT.
PIN
BU-61843(5) /
61743(5)
(4KK RAM)
PIN
BU-61864(5)
(64K RAM)
MISCELLANEOUS
SIGNAL NAME
57
26
57
-
DESCRIPTION
For factory test only. Do not connect for normal operation.
XCVR_TP (ZAP VOLTB)
XCVR_TP (RESET)
P2(*)
P3(*)
P4(*)
XCVR_TP (READOUTB)
XCVR_TP (CLOCK)
XCVR_TP (READOUTA)
FACTORY TEST
XCVR_TP (ZAP VOLTA)
P1(*)
SIGNAL NAME
PIN
P6(*)
P5(*)
(*) Note that the Test Output pins are recessed pads located on the bottom of the package.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-61865G4-122 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61688F0-110S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61688F0-110 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61688F0-120S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61688F0-120Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU-61865G3-100 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Telecommunication IC |
| BU-61865G3-110 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Telecommunication IC |
| BU-61865G4-100 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Telecommunication IC |
| BU-61865G4-110 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Telecommunication IC |
| BU-61XXX | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MINIATURE ADVANCED COMMUNICATION ENGINE (MINI-ACE) AND MINI-ACE PLUS |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。