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參數(shù)資料
| 型號： | BU-61865F4-162 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 X 1 INCH, 0.155 INCH HEIGHT, FP-72 |
| 文件頁數(shù)： | 28/56頁 |
| 文件大?。?/td> | 321K |
| 代理商： | BU-61865F4-162 |
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The Enhanced Mini-ACE built-in test may be initiated by a com-
mand from the host processor, via the START/REST REGIS-
TER. For RT mode, this may include the host processor invoking
self-test following receipt of an Initiate self-test mode command.
The results of the self-test are host accessible by means of the
BIT status register. For RT mode, the result of the self-test may
be communicated to the bus controller via bit 8 of the RT BIT
word ("0" = pass, "1" = fail).
Assuming that the protocol self-test passes, all of the register
and shared RAM locations will be restored to their state prior to
the self-test, with the exception of the 60 RAM address locations
0342-037D and the TIME TAG REGISTER. Note that for RT
mode, these locations map to the illegalization lookup table for
"broadcast transmit subaddresses 1 through 30" (non-mode
code subaddresses). Since MIL-STD-1553 does not define
these as valid command words, this section of the illegalization
lookup table is normally not used. The TIME TAG REGISTER will
continue to increment during the self-test.
If there is a failure of the protocol self-test, it is possible to access
information about the first failed vector. This may be done by
means of the Enhanced Mini-ACE's upper registers (register
addresses 32 through 63). Through these registers, it is possible
to determine the self-test ROM address of the first failed vector,
the expected response data pattern (from the ROM), the register
or memory address, and the actual (incorrect) data value read
from register or memory. The on-chip self-test ROM is 4K X 24.
Note that the RAM self-test is destructive. That is, following the
RAM self-test, regardless of whether the test passes or fails, the
shared RAM is not restored to its state prior to this test.
Following a failed RAM self-test, the host may read the internal
RAM to determine which location(s) failed the walking pattern
test.
RAM PARITY
The BC/RT/MT version of the Enhanced Mini-ACE is available
with options of 4K or 64K words of internal RAM. For the 64K
option, the RAM is 17 bits wide. The 64K X 17 internal RAM
allows for parity generation for RAM write accesses, and parity
checking for RAM read accesses. This includes host RAM acess-
es, as well as acesses by the Enhanced Mini-ACE’s internal
logic. When the Enhanced Mini-ACE detects a RAM parity error,
it reports it to the host processor by means of an interrupt and a
register bit. Also, for the RT and Selective Message Monitor
modes, the RAM address where a parity error was detected will
be stored on the Interrupt Status Queue (if enabled).
RELOCATABLE MEMORY MANAGEMENT LOCATIONS
In the Enhanced Mini-ACE's default configuration, there is a
fixed
area of shared RAM addresses, 0000h-03FF, that is allocated for
storage of the BC's or RT's pointers, counters, tables, and other
"non-message" data structures. As a means of reducing the
overall memory address space for using multiple Enhanced Mini-
ACEs in a given system (e.g., for use with the DMA interface
34
configuration), the Enhanced Mini-ACE allows this area of RAM
to be relocated by means of 6 configuration register bits. To pro-
vide backwards compatibility to ACE and Mini-ACE, the default
for this RAM area is 0000h-03FFh.
HOST PROCESSOR INTERFACE
The Enhanced Mini-ACE supports a wide variety of processor
interface configurations. These include shared RAM and DMA
configurations, straightforward interfacing for 16-bit and 8-bit
buses, support for both non-multiplexed and multiplexed
address/data buses, non-zero wait mode for interfacing to a
processor address/data buses, and zero wait mode for interfac-
ing (for example) to microcontroller I/O ports. In addition, with
respect to the ACE/Mini-ACE, the Enhanced Mini-ACE provides
two major improvements: (1) reduced maximum host access
time for shared RAM mode; and (2) increased maximum DMA
grant time for the transparent/DMA mode.
The Enhanced Mini-ACE's maximum host holdoff time (time prior
to the assertion of the
handshake signal) has been sig-
nificantly reduced. For ACE/Mini-ACE, this maximum holdoff
time is 10 internal word transfer cycles, resulting in an overall
holdoff time of approximately 2.8 s, using a 16 MHz clock. By
comparison, using the Enhanced Mini-ACE's ENHANCED CPU
ACCESS feature, this worst-case holdoff time is reduced signifi-
cantly, to a single internal transfer cycle. For example, when
operating the Enhanced Mini-ACE in its 16-bit buffered, non-zero
wait configuration with a 16 MHz clock input, this results in a
maximum overall host transfer cycle time of 632 ns for a read
cycle, or 570 ns for a write cycle.
In
addition,
for
using
the
ACE
or
Mini-ACE
in
the
transparent/DMA configuration, the maximum request-to-grant
time, which occurs prior to an RT start-of-message sequence, is
4.0 s with a 16 MHz clock, or 3.5 s with a 12 MHz clock. For
the Enhanced Mini-ACE functioning as a MIL-STD-1553B RT,
this time has been increased to 8.5 s at 10 MHz, 10 s at 16
MHz, 9 s at 12 MHz, and 10.5 s at 20MHz. This provides
greater flexibility, particularly for systems in which a host has to
arbitrate among multiple DMA requestors.
By far, the most commonly used processor interface configura-
tion is the 16-bit buffered, non-zero wait mode. This configuration
may be used to interface between 16-bit or 32-bit microproces-
sors and an Enhanced Mini-ACE. In this mode, only the
Enhanced Mini-ACE's internal 4K or 64K words of internal RAM
are used for storing 1553 message data and associated "house-
keeping" functions. That is, in this configuration, the Enhanced
Mini-ACE will never attempt to access memory on the host bus.
FIGURE 12 illustrates a generic connection diagram between a
16-bit (or 32-bit) microprocessor and an Enhanced Mini-ACE for
the 16-bit buffered configuration, while Figures 13 and 14, and
associated tables illustrate the processor read and write timing
respectively.
READYD
相關(guān)PDF資料 |
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| BU-61865F4-172Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61865F4-172Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61865F4-172Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61865F4-182S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61865F4-182 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
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