- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223462 > BU-61865F4-142Q (DATA DEVICE CORP) 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 PDF資料下載
參數(shù)資料
| 型號(hào)： | BU-61865F4-142Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 X 1 INCH, 0.155 INCH HEIGHT, FP-72 |
| 文件頁(yè)數(shù)： | 9/56頁(yè) |
| 文件大?。?/td> | 321K |
| 代理商： | BU-61865F4-142Q |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)當(dāng)前第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)
The op code parity bit encompasses all sixteen bits of the op
code word. This bit must be programmed for odd parity. If the
message sequence control processor fetches an undefined op
code word, an op code word with even parity, or bits 9-5 of an op
code word do not have a binary pattern of 01010, the message
sequence control processor will immediately halt the BC's oper-
ation. In addition, if enabled, a BC TRAP OP CODE interrupt will
be issued. Also, if enabled, a parity error will result in an OP
CODE PARITY ERROR interrupt.
TABLE 37 describes the Condition Codes.
17
TABLE 36. BC OPERATIONS FOR MESSAGE SEQUENCE CONTROL
INSTRUCTION MNEMONIC
OP CODE
(HEX)
PARAMETER
CONDITIONAL
OR
UNCONDITIONAL
DESCRIPTION
Interrupt
Request
Execute
Message
IRQ
XEQ
0006
0001
Interrupt
Bit Pattern
in 4 LS bits
Message Control /
Status Block
Address
Conditional
Generate an interrupt if the condition flag tests TRUE, otherwise
continue execution at the next OpCode in the instruction list.
The passed parameter (Interrupt Bit Pattern) specifies which of
the ENHANCED BC IRQ bit(s) (bits 5-2) will be set in Interrupt
Status Register #2. Only the four LSBs of the passed parameter
are used. A parameter where the four LSBs are logic "0" will
not generate an interrupt.
Executes the message at the specified Message Control/Status
Block Address if the condition flag tests TRUE, otherwise contin-
ue execution at the next OpCode in the instruction list.
Compare to
Frame Timer
Halt
Jump
CFT
HLT
JMP
000A
0007
0002
Delay Time Value
(Resolution
= 100S / LSB)
Not Used
(Don’t Care)
Instruction List
Addrss
Unconditional
Conditional
Compare Time Value to Frame Time Counter and set or clear
the LT and EQ flag based on the results of the compare.
Stop execution of the Message Sequence Control Program until
a new BC Start is issued by the host if the condition flag tests
TRUE, otherwise continue execution at the next OpCode in the
instruction list.
Jump to the OpCode specified in the Instruction List if the condi-
tion flag tests TRUE, otherwise continue execution at the next
OpCode in the instruction list.
Compare to
Message
Timer
Delay
Subroutine
Call
CMT
DLY
CAL
000B
0008
0003
Delay Time Value
(Resolution
= 1S / LSB)
Delay Time Value
(Resolution = 1S)
Instruction List
Addrss
Unconditional
Conditional
Compare Time Value to Message Time Counter and set or clear
the LT and EQ flag based on the results of the compare.
Delay the time specified by the Time parameter before executing
the next OpCode if the condition flag tests TRUE, otherwise
continue execution at the next OpCode without delay. The delay
generated will use the Time to Next Message Timer.
Jump to the OpCode specified by the Instruction List Address
and push the Address of the Next OpCode on the Call Stack if
the condition flag test TRUE, otherwise continue execution at
the next OpCode in the instruction list. Note that the maximum
depth of the subroutine call stack is four.
GP Flag Bits
Wait Until
Frame Timer
= 0
Subroutine
Retrn
FLG
WFT
RTN
000C
0009
0004
Used to set,
clear, or toggle GP
(General Purpose)
Flag bits
(See description)
Not Used
(Don’t Care)
Not Used
(Don’t Care)
Unconditional
Conditional
Used to set, toggle, or clear any or all of the eight general pur-
pose flags. The table below illustrates the use of the GP Flag
Bits instruction for the case of GP0 (General Purpose Flag 0).
Bits 1 and 9 of the parameter byte affect flag GP1, bits 2 and 10
effect GP2, etc., according to the following rules:
Wait until Frame Time counter is equal to Zero before continuing
execution of the Message Sequence Control Program if the
condition flag tests TRUE, otherwise continue execution at the
next OpCode without delay.
Return to the OpCode popped off the Call Stack if the condition
flag tests TRUE, otherwise continue execution at the next
OpCode in the instruction list.
Bit 8
0
1
0
1
0
1
Bit 0
Effect on GP0
No Change
Set Flag
Clear Flag
Toggle Flag
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-61865F4-142S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61865F4-142Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61865F4-152K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61865F4-152L | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61865F4-152S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU-61865G3-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU-61865G3-110 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU-61865G4-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU-61865G4-110 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU-61XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MINIATURE ADVANCED COMMUNICATION ENGINE (MINI-ACE) AND MINI-ACE PLUS |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。