
50
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
Rev. C
(*) Note that the Test Output pins are recessed pads located on the bottom of the package.
CLOCK_IN (I)
20 MHz, 16 MHz, 12 MHz, or 10 MHz clock input.
30
XCVR_TP
(ZAP VOLTA)
For factory test only. Do not connect for normal operation.
P1(*)
XCVR_TP
(READOUTB)
P2(*)
XCVR_TP
(READOUTA)
P3(*)
XCVR_TP
(CLOCK)
P4(*)
XCVR_TP
(RESET)
P5(*)
XCVR_TP
(ZAP VOLTB)
P6(*)
MSTCLR(I)
Master Clear. Negative true Reset input, normally asserted low following power turn-on. When coming out
of a “reset” condition, please note that the rise time of MSTCLR must be less than 10 s.
2
TX_INH_A (I)
Transmitter inhibit inputs for the Channel A and Channel B MIL-STD-1553 transmitters. For normal opera-
tion, these inputs should be connected to logic "0". To force a shutdown of Channel A and/or Channel B, a
value of logic "1" should be applied to the respective TX_INH input.
59
TX_INH_B (I)
60
TABLE 53. MISCELLANEOUS (CONT.)
SIGNAL NAME
DESCRIPTION
PIN
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
TABLE 54. FACTORY TEST
SIGNAL NAME
DESCRIPTION
PIN
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX