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參數(shù)資料
| 型號(hào)： | BU-61864G3-780Z |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 25.40 X 25.40 MM, 3.94 MM HEIGHT, CERAMIC, FP-72 |
| 文件頁數(shù)： | 41/60頁 |
| 文件大小： | 700K |
| 代理商： | BU-61864G3-780Z |
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46
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
Rev. C
SELECT (I)
61
Generally connected to a CPU address decoder output to select the Enhanced Mini-ACE for a transfer
to/from either RAM or register.
STRBD (I)
62
Strobe Data. Used in conjunction with SELECT to initiate and control the data transfer cycle between the
host processor and the ENHANCED MINI-ACE. STRBD must be asserted low through the full duration of
the transfer cycle.
RD / WR
63
Read/Write. For a host processor access, RD/WR selects between reading and writing. In the 16-bit
buffered mode, if POL_SEL is logic "0, then RD/WR should be low (logic “0") for read accesses and high
(logic "1") for write accesses. If POL_SEL is logic "1", or the interface is configured for a mode other than
16-bit buffered mode, then RD/WR is high (logic "1") for read accesses and low (logic "0") for write access-
es.
ADDR_LAT(I) /
MEMOE (O)
14
Memory Output Enable or Address Latch.
In buffered mode, the ADDR_LAT input is used to configure the buffers for A15-A0, SELECT, MEM/REG,
and MSB/LSB (for 8-bit mode only) in latched mode (when low) or transparent mode (when high). That is,
the Enhanced Mini-ACE's internal transparent latches will track the values on A15-A0, SELECT,
MEM/REG, and MSB/LSB when ADDR_LAT is high, and latch the values when ADDR_LAT goes low.
In general, for interfacing to processors with a non-multiplexed address/data bus, ADDR_LAT should be
hardwired to logic "1". For interfacing to processors with a multiplexed address/data bus, ADDR_LAT
should be connected to a signal that indicates a valid address when ADDR_LAT is logic "1".
In transparent mode, MEMOE output signal is used to enable data outputs for external RAM read cycles
(normally connected to the OE input signal on external RAM chips).
ZEROWAIT (I) /
MEMWR (O)
23
Memory Write or Zero Wait . In buffered mode, input signal (ZEROWAIT) used to select between the zero
wait mode (ZEROWAIT = “0") and the non-zero wait mode (ZEROWAIT = "1").
In transparent mode, active low output signal (MEMWR) asserted low during memory write transfers to
strobe data into external RAM (normally connected to the WR input signal on external RAM chips).
16 / 8 (I) /
DTREQ (O)
24
Data Transfer Request or Data Bus Select. In buffered mode, input signal 16/8 used to select between the
16 bit data transfer mode (16/8= "1") and the 8-bit data transfer mode (16/8 = "0").
In transparent mode (16-bit only), active low level output signal DTREQ used to request access to the
processor/RAM interface bus (address and data buses).
MSB / LSB (I) /
DTGRT (I)
64
Data Transfer Grant or Most Significant Byte/Least Significant Byte.
In 8-bit buffered mode, input signal (MSB/LSB) used to indicate which byte is currently being transferred
(MSB or LSB). The logic sense of MSB/LSB is controlled by the POL_SEL input. MSB/LSB is not used in
the 16-bit buffered mode.
In transparent mode, active low input signal (DTGRT) asserted in response to the DTREQ output to indi-
cate that control of the external processor/RAM bus has been transferred from the host processor to the
Enhanced Mini-ACE.
TABLE 51. PROCESSOR INTERFACE CONTROL
SIGNAL NAME
DESCRIPTION
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
PIN
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