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參數(shù)資料
| 型號(hào)： | BU-61864G3-130S |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 25.40 X 25.40 MM, 2.54 MM HEIGHT, CERAMIC, QFP-72 |
| 文件頁數(shù)： | 28/60頁 |
| 文件大小： | 457K |
| 代理商： | BU-61864G3-130S |
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34
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
F-10/02-300
For the Enhanced Mini-ACE/-ACE's Enhanced BC mode, there
are four user-defined interrupt bits. The BC Message Sequence
Control Engine includes an instruction enabling it to issue these
interrupts at any time.
For RT and Monitor modes, the Enhanced Mini-ACE/-ACE archi-
tecture includes an Interrupt Status Queue. This provides a mech-
anism for logging messages that result in interrupt requests.
Entries to the Interrupt Status Queue may be filtered such that only
valid and/or invalid messages will result in entries on the queue.
The Enhanced Mini-ACE/-ACE incorporates additional interrupt
conditions beyond ACE/Mini-ACE (Plus), based on the addition
of Interrupt Mask Register #2 and Interrupt Status Register #2.
This is accomplished by chaining the two Interrupt Status
Registers using the INTERRUPT CHAIN BIT (bit 0) in Interrupt
Status Register #2 to indicate that an interrupt has occurred in
Interrupt Status Register #1. Additional interrupts include "Self-
Test Completed", masking bits for the Enhanced BC Control
Interrupts, 50% Rollover interrupts for RT Command Stack, RT
Circular Buffers, MT Command Stack, and MT Data Stack; BC
Op Code Parity Error, (RT) Illegal Command, (BC) General
Purpose Queue or (RT/MT) Interrupt Status Queue Rollover,
Call Stack Pointer Register Error, BC Trap Op Code, and the four
User-Defined interrupts for the Enhanced BC mode.
BUILT-IN TEST
A salient feature of the Enhanced Mini-ACE/-ACE is its highly
autonomous self-test capability. This includes both protocol and
RAM self-tests. Either or both of these self-tests may be initiated
by command(s) from the host processor.
The protocol test consists of a comprehensive toggle test of the
terminal's logic. The test includes testing of all registers,
Manchester decoders, protocol logic, and memory management
logs. This test is completed in approximately 32,000 clock cycles.
That is, about 1.6 ms with a 20 MHz clock, 2.0 ms at 16 MHz, 2.7
ms at 12 MHz, and 3.2 ms at 10 MHz.
There is also a separate built-in test for the Enhanced Mini-ACE/-
ACE's 4K X 16 or 64K X 16 shared RAM. This test consists of writing
and then reading/verifying the two walking patterns "data = address"
and "data = address inverted". This test takes 10 clock cycles per
word. For an Enhanced Mini-ACE/-ACE with 4K words of RAM, this
is about 2.0 ms with a 20 MHz clock, 2.6 ms at 16 MHz, 3.4 ms at 12
MHz, or 4.1 ms at 10 MHz. For an Enhanced Mini-ACE/-ACE with
64K words of RAM, this test takes about 32.8 ms with a 20 MHz clock,
40.1 ms at 16 MHz, 54.6 ms at 12 MHz, or 65.6 ms at 10 MHz.
The Enhanced Mini-ACE/-ACE built-in protocol test is performed
automatically at power-up. In addition, the protocol or RAM self-
tests may be initiated by a command from the host processor, via
the START/REST REGISTER. For RT mode, this may include the
host processor invoking self-test following receipt of an Initiate
self-test mode command. The results of the self-test are host
accessible by means of the BIT status register. For RT mode, the
result of the self-test may be communicated to the bus controller
via bit 8 of the RT BIT word ("0" = pass, "1" = fail).
Assuming that the protocol self-test passes, all of the register
and shared RAM locations will be restored to their state prior to
the self-test, with the exception of the 60 RAM address locations
0342-037D and the TIME TAG REGISTER. Note that for RT
mode, these locations map to the illegalization lookup table for
"broadcast transmit subaddresses 1 through 30" (non-mode
code subaddresses). Since MIL-STD-1553 does not define
these as valid command words, this section of the illegalization
lookup table is normally not used during RT operation. The TIME
TAG REGISTER will continue to increment during the self-test.
If there is a failure of the protocol self-test, it is possible to access
information about the first failed vector. This may be done by means
of the Enhanced Mini-ACE/-ACE's upper registers (register
addresses 32 through 63). Through these registers, it is possible to
determine the self-test ROM address of the first failed vector, the
expected response data pattern (from the ROM), the register or
memory address, and the actual (incorrect) data value read from
register or memory. The on-chip self-test ROM is 4K X 24.
Note that the RAM self-test is destructive. That is, following the
RAM self-test, regardless of whether the test passes or fails, the
shared RAM is not restored to its state prior to this test. Following
a failed RAM self-test, the host may read the internal RAM to
determine which location(s) failed the walking pattern test.
RAM PARITY
The BC/RT/MT version of the Enhanced Mini-ACE/-ACE is avail-
able with options of 4K or 64K words of internal RAM. For the 64K
option, the RAM is 17 bits wide. The 64K X 17 internal RAM allows
for parity generation for RAM write accesses, and parity checking
for RAM read accesses. This includes host RAM accesses, as well
as accesses by the Enhanced Mini-ACE’s/-ACE’s internal logic.
When the Enhanced Mini-ACE/-ACE detects a RAM parity error,
it reports it to the host processor by means of an interrupt and a
register bit. Also, for the RT and Selective Message Monitor
modes, the RAM address where a parity error was detected will be
stored on the Interrupt Status Queue (if enabled).
RELOCATABLE MEMORY MANAGEMENT LOCATIONS
In the Enhanced Mini-ACE/-ACE's default configuration, there is
a
fixed area of shared RAM addresses, 0000h-03FF, that is allo-
cated for storage of the BC's or RT's pointers, counters, tables,
and other "non-message" data structures. As a means of reduc-
ing the overall memory address space for using multiple
Enhanced Mini-ACE/-ACE’s in a given system (e.g., for use with
the DMA interface configuration), the Enhanced Mini-ACE/-ACE
allows this area of RAM to be relocated by means of 6 configura-
tion register bits. To provide backwards compatibility to ACE and
Mini-ACE, the default for this RAM area is 0000h-03FFh.
HOST PROCESSOR INTERFACE
The Enhanced Mini-ACE/-ACE supports a wide variety of proces-
sor interface configurations. These include shared RAM and DMA
configurations, straightforward interfacing for 16-bit and 8-bit buses,
support for both non-multiplexed and multiplexed address/data
buses, non-zero wait mode for interfacing to a processor
address/data buses, and zero wait mode for interfacing (for example)
to microcontroller I/O ports. In addition, with respect to the ACE/Mini-
ACE, the Enhanced Mini-ACE provides two major improvements: (1)
reduced maximum host access time for shared RAM mode; and (2)
increased maximum DMA grant time for the transparent/DMA mode.
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