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          • 您現(xiàn)在的位置:買賣IC網(wǎng) > PDF目錄255899 > BU-61864F4-420K (DATA DEVICE CORP) 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 PDF資料下載
          參數(shù)資料
          型號(hào): BU-61864F4-420K
          廠商: DATA DEVICE CORP
          元件分類: 微控制器/微處理器
          英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
          封裝: 25.40 X 25.40 MM, 3.94 MM HEIGHT, CERAMIC, FP-72
          文件頁數(shù): 24/60頁
          文件大?。?/td> 457K
          代理商: BU-61864F4-420K
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          30
          Data Device Corporation
          www.ddc-web.com
          BU-6174X/6184X/6186X
          F-10/02-300
          MONITOR ARCHITECTURE
          The Enhanced Mini-ACE/-ACE includes three monitor modes:
          (1) A Word Monitor mode
          (2) A selective message monitor mode
          (3) A combined RT/message monitor mode
          For new applications, it is recommended that the selective mes-
          sage monitor mode be used, rather than the word monitor mode.
          Besides providing monitor filtering based on RT address, T/R bit,
          and subaddress, the message monitor eliminates the need to
          determine the start and end of messages by software.
          WORD MONITOR MODE
          In the Word Monitor Terminal mode, the Enhanced Mini-ACE/-
          ACE monitors both 1553 buses. After the software initialization
          and Monitor Start sequences, the Enhanced Mini-ACE/-ACE
          stores all Command, Status, and Data Words received from both
          buses. For each word received from either bus, a pair of words is
          stored to the Enhanced Mini-ACE/-ACE's shared RAM. The first
          word is the word received from the 1553 bus. The second word
          is the Monitor Identification (ID), or "Tag" word. The ID word con-
          tains information relating to bus channel, word validity, and inter-
          word time gaps. The data and ID words are stored in a circular
          buffer in the shared RAM address space.
          WORD MONITOR MEMORY MAP
          A typical word monitor memory map is illustrated in TABLE 43.
          TABLE 43 assumes a 64K address space for the Enhanced Mini-
          ACE/-ACE's monitor. The Active Area Stack pointer provides
          the address where the first monitored word is stored. In the
          example, it is assumed that the Active Area Stack Pointer for
          Area A (location 0100) is initialized to 0000. The first received
          data word is stored in location 0000, the ID word for the first word
          is stored in location 0001, etc.
          BUSY BIT
          The Enhanced Mini-ACE/-ACE RT provides two different meth-
          ods for setting the Busy status word bit: (1) globally, by means of
          Configuration Register #1; or (2) on a T/R-bit/subaddress basis,
          by means of a RAM lookup table. If the host CPU asserts the
          BUSY bit to logic ”0” in Configuration Register #1, the Enhanced
          Mini-ACE/-ACE RT will respond to all non-broadcast com-
          mands with the Busy bit set in its RT Status Word.
          Alternatively, there is a Busy lookup table in the Enhanced Mini-
          ACE/-ACE shared RAM. By means of this table, it is possible for
          the host processor to set the busy bit for any selectable subset
          of the 128 combinations of broadcast/own address, T/R bit, and
          subaddress.
          If the busy bit is set for a transmit command, the Enhanced Mini-
          ACE/-ACE RT will respond with the busy bit set in the status
          word, but will not transmit any data words. If the busy bit is set for
          a receive command, the RT will also respond with the busy sta-
          tus bit set. There are two programmable options regarding the
          reception of data words for a non-mode code receive command
          for which the RT is busy: (1) to transfer the received data words
          to shared RAM; or (2) to not transfer the data words to shared
          RAM.
          RT ADDRESS
          The Enhanced Mini-ACE/-ACE offers several different options
          for designating the Remote Terminal address. These include the
          following: (1) hardwired, by means of the 5 RT ADDRESS inputs,
          and the RT ADDRESS PARITY input; (2) by means of the RT
          ADDRESS (and PARITY) inputs, but latched via hardware, on
          the rising edge of the RT_AD_LAT input signal; (3) input by
          means of the RT ADDRESS (and PARITY) inputs, but latched via
          host software; and (4) software programmable, by means of an
          internal register. In all four configurations, the RT address is
          readable by the host processor.
          RT BUILT-IN-TEST (BIT) WORD
          The bit map for the Enhanced Mini-ACE/-ACE's internal RT
          Built-in-Test (BIT) Word is indicated in TABLE 42.
          RT AUTO-BOOT OPTION
          If utilized, the RT pin-programmable auto-boot option allows the
          Enhanced Mini-ACE/-ACE RT to automatically initialize as an
          active remote terminal with the Busy status word bit set to logic
          "1" immediately following power turn-on. This is a useful feature
          for MIL-STD-1760 applications, in which the RT is required to be
          responding within 150 ms after power-up. This feature is avail-
          able for versions of the Enhanced Mini-ACE/-ACE with 4K
          words of RAM.
          OTHER RT FEATURES
          The Enhanced Mini-ACE/-ACE includes options for the
          Terminal flag status word bit to be set either under software con-
          trol and/or automatically following a failure of the loopback self-
          test. Other software programmable RT options include software
          programmable RT status and RT BIT words, automatic clearing
          of the Service Request bit following receipt of a Transmit vector
          word mode command, options regarding Data Word transfers for
          the Busy and Message error (illegal) Status word bits, and
          options for the handling of 1553A and reserved mode codes.
          COMMAND WORD CONTENTS ERROR
          0(LSB)
          RT-to-RT 2ND COMMAND WORD ERROR
          1
          RT-to-RT NO RESPONSE ERROR
          2
          TRANSMITTER SHUTDOWN B
          RT-to-RT GAP / SYNC ADDRESS ERROR
          3
          PARITY / MANCHESTER ERROR RECEIVED
          4
          INCORRECT SYNC RECEIVED
          5
          LOW WORD COUNT
          6
          HIGH WORD COUNT
          7
          BIT TEST FAILURE
          8
          TERMINAL FLAG INHIBITED
          9
          TRANSMITTER SHUTDOWN A
          10
          HANDSHAKE FAILURE
          12
          LOOP TEST FAILURE A
          13
          LOOP TEST FAILURE B
          14
          TRANSMITTER TIMEOUT
          15(MSB)
          DESCRIPTION
          BIT
          11
          TABLE 42. RT BIT WORD
          相關(guān)PDF資料
          PDF描述
          BU-61864F4-420L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
          BU-61864F4-420Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
          BU-61864F4-420S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
          BU-61864F4-420Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
          BU-61864F4-430L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
          相關(guān)代理商/技術(shù)參數(shù)
          參數(shù)描述
          BU-61864G3-100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
          BU-61864G3-110 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
          BU-61864G4-100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
          BU-61864G4-110 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
          BU-61864G4-200 制造商:DDC 功能描述:MIL-STD-1553/ARINC BUS CONTROLLER/RTU, 72 Pin, QFP
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