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    參數(shù)資料
    

    


    


    
型號(hào)：
BU-61864F3-132S

    

    
廠商：
DATA DEVICE CORP

    

    
元件分類(lèi)：
微控制器/微處理器

    

    
英文描述：
2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72

    

    
封裝：
25.40 X 25.40 MM, 3.94 MM HEIGHT, CERAMIC, FP-72

    

    
文件頁(yè)數(shù)：
32/60頁(yè)

    

    
文件大?。?/td>
457K

    

    
代理商：
BU-61864F3-132S


    

    

    

	
    
    
    

    
    
	
    38
    Data Device Corporation
    www.ddc-web.com
    BU-6174X/6184X/6186X
    F-10/02-300
    CLOCK IN
    t1
    t6
    t7
    t2
    t3
    t18
    t16
    VALID
    t8
    t9
    t14
    t15
    t17
    VALID
    t12
    t10
    t4
    t11
    t5
    VALID
    t13
    SELECT
    (Note 2,7)
    (Note 2)
    (Note 3,4,7)
    (Note 4,5)
    STRBD
    MEM/REG
    RD/WR
    IOEN
    (Note 2,6)
    (Note 6)
    (Note 9,10)
    (Note 7,8,9,10)
    READYD
    A15-A0
    D15-D0
    FIGURE 14. CPU WRITING RAM / REGISTER (16-BIT BUFFERED, NONZERO WAIT)
    NOTES:
    1.
    For the 16-bit buffered nonzero wait configuration TRANSPARENT/BUFFERED must be connected to logic "0", ZERO_WAIT and DTREG / 16/8
    must be connected to logic "1". The inputs TRIGGER_SEL and MSB/LSB may be connected to either +5V or ground.
    2.
    SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT  STRBD is sampled low (satisfying t1)
    and the Enhanced Mini-ACE/-ACE's protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low,
    starting the transfer cycle. After IOEN goes low, SELECT may be released high.
    3.
    MEM/REG must be presented high for memory access, low for register access.
    4.
    MEM/REG and RD/WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM/REG and
    RD/WR become latched internally.
    5.
    The logic sense for RD/WR in the diagram assumes that POLARITY_SEL is connected to logic "1". If POLARITY_SEL is connected to logic "0",
    RD/WR must be asserted high to write.
    6.
    The timing for the IOEN and READYD outputs assume a 50 pf load. For loading above 50 pf, the validity of IOEN and READYD is delayed by an
    additional 0.14 ns/pf typ, 0.28 ns/pf max.
    7.
    The timing for A15-A0, MEM/REG, and SELECT assumes that ADDR-LAT is connected to logic "1". Refer to Address Latch timing for additional
    details.
    9.
    The address bus A15-A0 and data bus D15-D0 are internally buffered transparently until the first rising edge of CLK after IOEN goes low. After
    this CLK edge, A15-A0 and D15-D0 become latched internally.
    10
    Setup time given for use in worst case timing calculations. None of the Enhanced Mini-ACE/-ACE input signals are required to be synchronized
    to the system clock. When SELECT and STRBD do not meet the setup time of t1, but occur during the setup time of an internal flip-flop, an addi-
    tional clock cycle may be inserted between the falling clock edge that latches MEM/REG and RD/WR and the rising clock edge that latches the
    address (A15-A0) and data (D15-D0). When this occurs, the delay from IOEN falling to READYD falling (t14) increases by one clock cycle and the
    address and data hold time (t12 and t13) must be increased by one clock.
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
BU-61864F3-142K
2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72

    

    
BU-61864F3-160
2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72

    

    
BU-61864F3-162L
2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72

    

    
BU-61864F4-172Z
2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72

    

    
BU-61864F4-182
2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
BU-61864F4-100
 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Telecommunication IC

    

    
BU-61864F4-110
 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Telecommunication IC

    

    
BU-61864G3-100
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BU-61864G3-110
 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Telecommunication IC

    

    
BU-61864G4-100
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