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參數(shù)資料
| 型號： | BU-61845G4-580L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 25.40 X 25.40 MM, 3.94 MM HEIGHT, CERAMIC, FP-72 |
| 文件頁數(shù)： | 30/60頁 |
| 文件大?。?/td> | 700K |
| 代理商： | BU-61845G4-580L |
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36
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
Rev. C
CLOCK IN
VALID
t7
t3
t8
t11
t13
t15
VALID
t10
t4
t9
t12
t19
;
;;
VALID
t16
t17
SELECT
(Note 2,7)
(Note 2)
(Note 3,4,7)
(Note 4,5)
STRBD
MEM/REG
RD/WR
IOEN
(Note 2,6)
(Note 6)
(Note 7,8,9)
READYD
A15-A0
D15-D0
;
;;
;;;
;;
t5
t1
t2
t6
t14
t18
FIGURE 13. CPU READING RAM / REGISTER (16-BIT BUFFERED, NONZERO WAIT)
NOTES:
1.
For the 16-bit buffered nonzero wait configuration, TRANSPARENT/BUFFERED must be connected to logic "0". ZERO_WAIT and DTREQ / 16/8
must be connected to logic "1". The inputs TRIGGER_SEL and MSB/LSB may be connected to either +5V or ground.
2.
SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT STRBD is sampled low (satisfying t1)
and the Enhanced Mini-ACE's protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low, start-
ing the transfer cycle. After IOEN goes low, SELECT may be released high.
3.
MEM/REG must be presented high for memory access, low for register access.
4.
MEM/REG and RD/WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM/REG and
RD/WR become latched internally.
5.
The logic sense for RD/WR in the diagram assumes that POLARITY_SEL is connected to logic "1." If POLARITY_SEL is connected to logic "0,"
RD/WR must be asserted low to read.
6.
The timing for IOEN, READYD and D15-D0 assumes a 50 pf load. For loading above 50 pf, the validity of IOEN, READYD, and D15-D0 is delayed
by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
7.
The timing for A15-A0, MEM/REG and SELECT assumes that ADDR-LAT is connected to logic "1." Refer to Address Latch timing for additional
details.
8.
The address bus A15-A0 is internally buffered transparently until the first rising edge of CLK after IOEN goes low. After this CLK edge, A15-A0
become latched internally.
9.
Setup time given for use in worst case timing calculations. None of the Enhanced Mini-ACE input signals are required to be synchronized to the
system clock. When SELECT and STRBD do not meet the setup time of t1, but occur during the setup window of an internal flip-flop, an addi-
tional clock cycle will be inserted between the falling clock edge that latches MEM/REG and RD/WR and the rising clock edge that latches the
Address (A15-A0). When this occurs, the delay from IOEN falling to READYD falling (t11) increases by one clock cycle and the address hold time
(t10) must be increased be one clock cycle.
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