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參數(shù)資料
| 型號： | BU-61845G3-582Z |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 25.40 X 25.40 MM, 3.94 MM HEIGHT, CERAMIC, FP-72 |
| 文件頁數(shù)： | 44/60頁 |
| 文件大?。?/td> | 700K |
| 代理商： | BU-61845G3-582Z |
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49
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
Rev. C
UPADDREN
(BU-6174X,
BU-6184X only)
For BU-61864/61865FX/GX, this pin signal is +5V-RAM and MUST be connected to +5V.
For BU-6174X and 6184X, this signal is used to control the function of the upper 4 address inputs (A15-
A12). For these versions of Enhanced Mini-ACE, if UPADDREN is connected to logic "1", then these four
signals operate as address lines A15-A12.
For BU-6184X/6174X, if UPADDREN is connected to logic "0", then A15 and A14 function as CLK_SEL_1
and CLK_SEL_0 respectively; A13 MUST be connected to Vcc-LOGIC (+5V or +3.3V); and A12 functions
as RTBOOT.
26
INT (O)
Interrupt Request output. If the LEVEL/PULSE interrupt bit (bit 3) of Configuration Register #2 is logic "0",
a negative pulse of approximately 500ns in width is output on INT to signal an interrupt request.
If LEVEL/PULSE is high, a low level interrupt request output will be asserted on INT. The level interrupt
will be cleared (high) after either: (1) The processor writes a value of logic "1" to INTERRUPT RESET, bit
2 of the Start/Reset Register; or (2) If bit 4 of Configuration Register #2, INTERRUPT STATUS AUTO-
CLEAR is logic "1", then it will only be necessary to read the Interrupt Status Register (#1 and/or #2) that
is requesting an interrupt that has been enabled by the corresponding Interrupt Mask Register. However,
for the case where both Interrupt Status Register #1 and Interrupt Status Register #2 have bits set reflect-
ing interrupt events, it will be necessary to read both interrupt status registers in order to clear INT.
57
INCMD (O) /
MCRST (O)
In-command or Mode Code Reset. The function of this pin is controlled by bit 0 of Configuration Register
#7, MODE CODE RESET/INCMD SELECT.
If this register bit is logic "0" (default), INCMD will be active on this pin. For BC, RT, or Selective Message
Monitor modes, INCMD is asserted low whenever a message is being processed by the Enhanced Mini-
ACE. In Word Monitor mode, INCMD will be asserted low for as long as the monitor is online.
active. In this case, MCRST will be asserted low for two clock cycles following receipt of a Reset remote
terminal mode command.
In BC or Monitor modes, if MODE CODE RESET/INCMD SELECT is logic "1", this signal is inoperative;
i.e., in this case, it will always output a value of logic "1".
25
TABLE 53. MISCELLANEOUS
SIGNAL NAME
DESCRIPTION
PIN
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
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| BU-61845G3-612W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61845G3-612Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61845G3-650S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61845G3-670K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
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相關(guān)代理商/技術(shù)參數(shù) |
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| BU-61845G4-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU-61845G4-110 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU-61860B3NEW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |μ-ACE (Micro-ACE?) |
| BU-61864 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |Enhanced Mini-ACE? |
| BU-61864F3-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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