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參數(shù)資料
| 型號(hào)： | BU-61843G3-660L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 25.40 X 25.40 MM, 3.94 MM HEIGHT, CERAMIC, FP-72 |
| 文件頁數(shù)： | 56/60頁 |
| 文件大?。?/td> | 700K |
| 代理商： | BU-61843G3-660L |
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6
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
Rev. C
address/data buses. In addition, with respect to ACE/Mini-ACE
(Plus), the worst case processor wait time has been significant-
ly reduced. For example, assuming a 16 MHz clock, this time has
been reduced from 2.8 s to 632 ns for read accesses, and to
570 ns for write accesses.
The Enhanced Mini-ACE series terminals operate over the full
military temperature range of -55 to +125°C. Available screened
to MIL-PRF-38534C, the terminals are ideal for military and
industrial processor-to-1553 applications.
TRANSCEIVERS
The transceivers in the Enhanced Mini-ACE series terminals are
fully monolithic, requiring only a +5 volt power input. The trans-
mitters are voltage sources, which provide improved line driving
capability over current sources. This serves to improve perfor-
mance on long buses with many taps. The transmitters also offer
an option which satisfies the MIL-STD-1760 requirement for a
minimum of 20 volts peak-to-peak, transformer coupled output.
Besides eliminating the demand for an additional power supply,
the use of a +5V only transceiver requires the use of a step-up,
rather than a step-down, isolation transformer. This provides the
advantage of a higher terminal input impedance than is possible
for a 15 volt or 12 volt transmitter. As a result, there is a greater
margin for the input impedance test, mandated for the 1553 val-
idation test. This characteristic allows for longer cable lengths
between a system connector and the isolation transformers of an
embedded 1553 terminal.
To provide compatibility to McAir specs, the Enhanced Mini-
ACEs are available with an option for transmitters with increased
rise and fall times.
Additionally, for MIL-STD-1760 applications, the Enhanced Mini-
ACE provides an option for a minimum stub voltage level of 20
volts peak-to-peak, transformer coupled.
The receiver sections of the Enhanced Mini-ACE are fully compli-
ant with MIL-STD-1553B Notice 2 in terms of front end overvoltage
protection, threshold, common mode rejection, and word error rate.
REGISTER AND MEMORY ADDRESSING
The software interface of the Enhanced Mini-ACE to the host
processor consists of 24 internal operational registers for normal
operation, an additional 24 test registers, plus 64K words of
shared memory address space. The Enhanced Mini-ACE's 4K X
16 or 64K X 17 internal RAM resides in this address space.
For normal operation, the host processor only needs to access
the lower 32 register address locations (00-1F). The next 32
locations (20-3F) should be reserved, since many of these are
used for factory test.
INTERNAL REGISTERS
The address mapping for the Enhanced Mini-ACE registers is
illustrated in TABLE 2.
BC General Purpose Queue Pointer /
RT-MT Interrupt Status Queue Pointer Register
(RD/WR)
1
BC General Purpose Flag Register (WR)
Interrupt Mask Register #2 (RD/WR)
RESERVED
1
0
1
0
1
0
1
0
1
Interrupt Status Register #2 (RD)
BC Condition Code Register (RD)
BIT Test Status Register (RD)
Configuration Register #7 (RD/WR)
0
1
0
1
0
1
0
1
0
1
Configuration Register #6 (RD/WR)
0
1
Test Mode Register 7
1
0
1
Test Mode Register 6
Test Mode Register 4
Test Mode Register 2
0
1
0
1
0
1
Test Mode Register 5
Test Mode Register 3
Test Mode Register 1
1
0
1
0
1
0
1
Test Mode Register 0
0
1
RT BIT Word Register (RD)
1
0
RT Status Word Register (RD)
0
1
0
Non-Enhanced BC Frame Time / Enhanced BC
Initial Instruction Pointer / RT Last Command /
MT Trigger Word Register(RD/WR)
1
0
1
0
BC Time Remaining to Next Message Register
(RD)
0
1
0
BC Frame Time Remaining Register (RD)
1
0
1
0
RT / Monitor Data Stack Address Register (RD)
0
1
0
1
0
Configuration Register #5 (RD/WR)
1
0
1
0
Configuration Register #4 (RD/WR)
0
1
0
Configuration Register #3 (RD/WR)
1
0
Interrupt Status Register #1 (RD)
0
1
0
Time Tag Register (RD/WR)
1
0
1
0
BC Control Word /
RT Subaddress Control Word Register (RD/WR)
0
1
0
Non-Enhanced BC/RT Command Stack Pointer /
Enhanced BC Instruction List Pointer Register
(RD)
1
0
Start/Reset Register (WR)
1
0
Configuration Register #2 (RD/WR)
0
1
0
Configuration Register #1 (RD/WR)
1
0
Interrupt Mask Register #1 (RD/WR)
0
A0
A1
A2
A3
A4
REGISTER
DESCRIPTION/ACCESSIBILITY
ADDRESS LINES
TABLE 2. ADDRESS MAPPING
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