參數(shù)資料
      型號: BU-61843G3-520Q
      廠商: DATA DEVICE CORP
      元件分類: 微控制器/微處理器
      英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
      封裝: 25.40 X 25.40 MM, 2.54 MM HEIGHT, CERAMIC, QFP-72
      文件頁數(shù): 8/60頁
      文件大?。?/td> 457K
      代理商: BU-61843G3-520Q
      16
      Data Device Corporation
      www.ddc-web.com
      BU-6174X/6184X/6186X
      F-10/02-300
      BUS CONTROLLER (BC) ARCHITECTURE
      The BC functionality for the Enhanced Mini-ACE/-ACE includes
      two separate architectures: (1) the older, non-Enhanced Mode,
      which provides complete compatibility with the previous ACE
      and Mini-ACE (Plus) generation products; and (2) the newer,
      Enhanced BC mode. The Enhanced BC mode offers several new
      powerful architectural features. These include the incorporation
      of a highly autonomous BC message sequence control engine,
      which greatly serves to offload the operation of the host CPU.
      The Enhanced BC's message sequence control engine provides
      a high degree of flexibility for implementing major and minor
      frame scheduling; capabilities for inserting asynchronous mes-
      sages in the middle of a frame; to separate 1553 message data
      from control/status data for the purpose of implementing double
      buffering and performing bulk data transfers; for implementing
      message retry schemes, including the capability for automatic
      bus channel switchover for failed messages; and for reporting
      various conditions to the host processor by means of 4 user-
      defined interrupts and a general purpose queue.
      In both the non-Enhanced and Enhanced BC modes, the
      Enhanced Mini-ACE/-ACE BC implements all MIL-STD-1553B
      message formats. Message format is programmable on a mes-
      sage-by-message basis by means of the BC Control Word and
      the T/R bit of the Command Word for the respective message.
      The BC Control Word allows 1553 message format, 1553A/B
      type RT, bus channel, self-test, and Status Word masking to be
      specified on an individual message basis. In addition, automatic
      retries and/or interrupt requests may be enabled or disabled for
      individual messages. The BC performs all error checking
      required by MIL-STD-1553B. This includes validation of
      response time, sync type and sync encoding, Manchester II
      encoding, parity, bit count, word count, Status Word RT Address
      field, and various RT-to-RT transfer errors. The Enhanced Mini-
      ACE/-ACE BC response timeout value is programmable with
      choices of 18, 22, 50, and 130 s. The longer response timeout
      values allow for operation over long buses and/or the use of
      repeaters.
      In its non-Enhanced Mode, the Enhanced Mini-ACE/-ACE may
      be programmed to process BC frames of up to 512 messages
      with no processor intervention. In the Enhanced BC mode, there
      is no explicit limit to the number of messages that may be
      processed in a frame. In both modes, it is possible to program for
      either single frame or frame auto-repeat operation. In the auto-
      repeat mode, the frame repetition rate may be controlled either
      internally, using a programmable BC frame timer, or from an
      external trigger input.
      ENHANCED BC MODE: MESSAGE SEQUENCE CONTROL
      One of the major new architectural features of the Enhanced
      Mini-ACE/-ACE series is its advanced capability for BC mes-
      sage sequence control. The Enhanced Mini-ACE/-ACE sup-
      ports highly autonomous BC operation, which greatly offloads
      the operation of the host processor.
      The operation of the Enhanced Mini-ACE/-ACE's message
      sequence control engine is illustrated in FIGURE 2. The BC mes-
      sage sequence control involves an instruction list pointer register;
      an instruction list which contains multiple 2-word entries; a mes-
      sage control/status stack, which contains multiple 8-word or 10-
      word descriptors; and data blocks for individual messages.
      The initial value of the instruction list pointer register is initialized
      by the host processor (via Register 0D), and is incremented by
      the BC message sequence processor (host readable via
      Register 03). During operation, the message sequence control
      processor fetches the operation referenced by the instruction list
      pointer register from the instruction list.
      Note that the pointer parameter referencing the first word of a
      message's control/status block (the BC Control Word) must con-
      FIGURE 2. BC MESSAGE SEQUENCE CONTROL
      OP CODE
      DATA BLOCK
      MESSAGE
      CONTROL/STATUS
      PARAMETER
      (POINTER)
      BLOCK
      BC INSTRUCTION
      LIST
      BC INSTRUCTION
      LIST POINTER REGISTER
      BC CONTROL
      WORD
      COMMAND WORD
      (Rx Command for
      RT-to-RT transfer)
      DATA BLOCK POINTER
      TIME-TO-NEXT MESSAGE
      TIME TAG WORD
      BLOCK STATUS WORD
      LOOPBACK WORD
      RT STATUS WORD
      2nd (Tx) COMMAND WORD
      (for RT-to-RT transfer)
      2nd RT STATUS WORD
      (for RT-to-RT transfer)
      INITIALITIZE BY REGISTER
      0D (RD/WR); READ CURRENT
      VALUE VIA REGISTER 03
      (RD ONLY)
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