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參數(shù)資料
| 型號(hào)： | BU-61843G3-192Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 25.40 X 25.40 MM, 2.54 MM HEIGHT, CERAMIC, QFP-72 |
| 文件頁數(shù)： | 46/60頁 |
| 文件大小： | 457K |
| 代理商： | BU-61843G3-192Q |
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50
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
F-10/02-300
UPADDREN
(BU-6174X,
BU-6184X only)
UPADDREN
For BU-61864/61865FX/GX, this pin signal is +5V-RAM and
MUST be connected to +5V.
For the 61860BX, this signal must be connected to logic "1".
For BU-6174X and 6184X, this signal is used to control the func-
tion of the upper 4 address inputs (A15-A12). For these versions of
Enhanced Mini-ACE/-ACE, if UPADDREN is connected to logic
"1", then these four signals operate as address lines A15-A12.
For BU-6184X/6174X, if UPADDREN is connected to logic "0",
then A15 and A14 function as CLK_SEL_1 and CLK_SEL_0
respectively; A13 MUST be connected to Vcc-LOGIC (+5V or
+3.3V); and A12 functions as RTBOOT.
26
N2
-
MCRST (O)
For RT mode MCRST will be asserted low for two clock cycles fol-
lowing receipt of a Reset remote terminal mode command.
-
A13
INT (O)
Interrupt Request output. If the LEVEL/PULSE interrupt bit (bit 3)
of Configuration Register #2 is logic "0", a negative pulse of
approximately 500ns in width is output on INT to signal an inter-
rupt request.
If LEVEL/PULSE is high, a low level interrupt request output will
be asserted on INT. The level interrupt will be cleared (high) after
either: (1) The processor writes a value of logic "1" to INTERRUPT
RESET, bit 2 of the Start/Reset Register; or (2) If bit 4 of
Configuration Register #2, INTERRUPT STATUS AUTO-CLEAR is
logic "1", then it will only be necessary to read the Interrupt Status
Register (#1 and/or #2) that is requesting an interrupt that has
been enabled by the corresponding Interrupt Mask Register.
However, for the case where both Interrupt Status Register #1 and
Interrupt Status Register #2 have bits set reflecting interrupt
events, it will be necessary to read both interrupt status registers
in order to clear INT.
57
A18
-
INCMD (O)
For BC, RT, or Selective Message Monitor modes, INCMD is
asserted low whenever a message is being processed by the
-ACE. In Word Monitor mode, INCMD will be asserted low for as
long as the monitor is online.
-
M1
INCMD (O) /
MCRST (O)
-
In-command or Mode Code Reset. The function of this pin is con-
trolled by bit 0 of Configuration Register #7, MODE CODE
RESET/INCMD SELECT.
If this register bit is logic "0" (default), INCMD will be active on this
pin. For BC, RT, or Selective Message Monitor modes, INCMD is
asserted low whenever a message is being processed by the
Enhanced Mini-ACE. In Word Monitor mode, INCMD will be assert-
ed low for as long as the monitor is online.
For RT mode, if MODE CODE RESET/INCMD SELECT is pro-
grammed to logic "1", MCRST will be active. In this case, MCRST
will be asserted low for two clock cycles following receipt of a
Reset remote terminal mode command.
In BC or Monitor modes, if MODE CODE RESET/INCMD SELECT
is logic "1", this signal is inoperative; i.e., in this case, it will always
output a value of logic "1".
25
-
TABLE 53. MISCELLANEOUS
SIGNAL NAME
DESCRIPTION
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BALL
PIN
BU-61860BX
BU-61840BX
BU-61740BX
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BU-61860BX
BU-61840BX
BU-61740BX
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