參數(shù)資料
型號(hào): BU-61843G3-100
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 2/32頁
文件大?。?/td> 833K
代理商: BU-61843G3-100
2
D
w
B
C
FIGURE 1. BU-61559 BLOCK DIAGRAM
8
7
5
4
(ILLEGALIZATION
ENABLE)
ILLENA
BUS-25679
1
2
3
LOW-POWER
TRANSCEIVER
A
TX_INH_A
8
7
5
4
BUS-25679
1
2
3
LOW-POWER
TRANSCEIVER
A
TX_INH_A
(RT ADDRESS)
RTAD 4-
, RTADP
(BROADCAST
ENABLE)
BRO_ENA
RTFAIL
(RTFAIL,
RTFLAG)
RTFLAG
(BROADCAST,
MESSAGE
TIMING, DATA
STROBE AND ERROR
INDICATORS)
BCSTRCV, CMD_STR, TXDTA_STR
RXDTA_STR, MSG_ERR, INCMD
ILLEGALLIZATION
LOGIC
DUAL
ENCODER/
DECODER
BC/RT/MT
PROTOCOL
8K x 16
DUAL
PORT
RAM
MEMORY DATA
MEMORY ADDRESS
MEMORY
MANAGEMENT,
SHARED
RAM/
PROCESSOR
INTERFACE,
INTERRUPT
LOGIC
TAGCLK
SSFLAG
MEMENA-IN
MEMEN-OUT,MEMWR, MEMOE
INT
IOEN, READYD
TRANSPARENT/BUFFERED, MSTCLR,
STRBD, SELECT, MEM/REG, RD/WR
(TIME TAG
CLOCK)
(SUBSYSTEM
FLAG)
(MEMORY
CONTROL)
(INTERRUPT
REQUEST)
(PROCESSOR
CONTROL)
ADDRESS
LATCHES/
BUFFERS*
ADDR_LAT
A15-A
D15-D
DATA
BUFFERS*
CLK IN (16MHz)
(PROCESSOR
DATA)
(PROCESSOR
ADDRESS)
(ADDRESS
LATCH
CONTROL)
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