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    參數(shù)資料
    型號: BU-61743G4-680L
    廠商: DATA DEVICE CORP
    元件分類: 微控制器/微處理器
    英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
    封裝: 25.40 X 25.40 MM, 3.94 MM HEIGHT, CERAMIC, FP-72
    文件頁數(shù): 40/60頁
    文件大小: 700K
    代理商: BU-61743G4-680L
    45
    Data Device Corporation
    www.ddc-web.com
    BU-6174X/6184X/6186X
    Rev. C
    A11
    3
    Lower 12 bits of 16-bit bi-directional address bus. In both the buffered and transparent
    modes, the host CPU accesses the Enhanced Mini-ACE registers and internal RAM by
    means of A11 - A0 (4K version). For the 64K versions, A15 - A12 are also used for this
    purpose.
    In buffered mode, A12-A0 (or A15-A0) are inputs only. In the transparent mode, A12-
    A0 (or A15-A0) are inputs during CPU accesses and become outputs, driving outward
    (towards the CPU) when the 1553 protocol/memory management logic accesses up to
    64K words of external RAM.
    In transparent mode, the address bus is driven outward only when the signal DTACK is
    low (indicating that the Enhanced Mini-ACE has control of the RAM interface bus) and
    IOEN is high, indicating a non-host access. Most of the time, including immediately after
    power turn-on, A12-A0 (or A15-A0) will be in high impedance (input) state.
    A10
    4
    A9
    69
    A8
    6
    A7
    11
    A6
    22
    A5
    68
    A4
    9
    A3
    10
    A2
    12
    A1
    27
    A0 (LSB)
    15
    TABLE 50. PROCESSOR ADDRESS BUS (CONT.)
    SIGNAL NAME
    DESCRIPTION
    BU-6186XFX/GX
    BU-6184XFX/GX
    BU-6174XFX/GX
    PIN
    4K RAM
    64K RAM
    A12 / RTBOOT
    70
    For BU-6186X (64K RAM versions), this signal is always configured as address line
    A12. Refer to the description for A11-A0 below.
    For BU-6184X/6174X (4K RAM versions), if UPADDREN is connected to logic "1", this
    signal operates as A12.
    For BU-6184X/6174X (4K RAM versions), if UPADDREN is connected to logic "0",
    then this signal functions as RTBOOT. If RTBOOT is connected to logic "0", the
    Enhanced Mini-ACE will initialize in RT mode with the Busy status word bit set follow-
    ing power turn-on. If RTBOOT hardwired to logic "1", the Enhanced Mini-ACE will ini-
    tialize in either Idle mode (for an RT-only part), or in BC mode (for a BC/RT/MT part).
    A12
    相關(guān)PDF資料
    PDF描述
    BU-61743G4-680S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
    BU-61743G4-680 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
    BU-61743G4-690L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
    BU-61743G4-690S 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
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