參數(shù)資料
型號(hào)： BU-61743G3-430K
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝： 25.40 X 25.40 MM, 2.54 MM HEIGHT, CERAMIC, QFP-72
文件頁(yè)數(shù)： 47/60頁(yè)
文件大?。?/td> 457K
代理商： BU-61743G3-430K
51
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
F-10/02-300
CLOCK_IN (I)
20 MHz, 16 MHz, 12 MHz, or 10 MHz clock input.
30
V9
-
TAG_CLK (I)
Time Tag Clock - External clock that may be used to increment the
Time Tag Register. This option is selected by setting Bits 7,8 and 9
of Configuration Register # 2 to Logic "1".
-
B18
-
RSTBITEN (I)
If this input is set to logic "1", the Built-In-Self-Test (BIST) will be
enabled after hardware reset (for example, following power-up). A
logic "0" input disables power-up BIST.
-
P17
MSTCLR(I)
Master Clear. Negative true Reset input, normally asserted low fol-
lowing power turn-on.
2
B11
TX_INH_A (I)
Transmitter inhibit inputs for the Channel A and Channel B MIL-
STD-1553 transmitters. For normal operation, these inputs should
be connected to logic "0". To force a shutdown of Channel A
and/or Channel B, a value of logic "1" should be applied to the
respective TX_INH input.
59
A14
TX_INH_B (I)
60
A15
TABLE 53. MISCELLANEOUS (CONT.)
SIGNAL NAME
DESCRIPTION
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BALL
PIN
BU-61860BX
BU-61840BX
BU-61740BX
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BU-61860BX
BU-61840BX
BU-61740BX
(*) Note that the Test Output pins are recessed pads located on the bottom of the package.
NC
No user connection
P1, P2, P3,
P4, P5, P6
B2, C1, C2, J1,
J2, K1, K2, M2,
N1, P1, P2, R1,
R2, R17, R18, T1,
U1, U2, U5, U10
U11, V5, V10, V11
TABLE 54. NO USER CONNECTIONS
SIGNAL NAME
DESCRIPTION
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BALL
PAD (*)
BU-61860BX
BU-61840BX
BU-61740BX
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BU-61860BX
BU-61840BX
BU-61740BX
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