參數(shù)資料
型號(hào): BU-61705G3-130Y
廠商: DATA DEVICE CORP
元件分類(lèi): 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝: CERAMIC, QFP-72
文件頁(yè)數(shù): 22/54頁(yè)
文件大小: 576K
代理商: BU-61705G3-130Y
29
Data Device Corporation
www.ddc-web.com
BU-61703/61705
D1 web-09/02-0
NOTES:
(1)
During Auto-Configuration the SSRT samples data three clock cycles following the falling edge of DTACK.
(2)
If self-test mode is not enabled, then RTACTIVE will go active high 1 clock cycle following the rising edge of DTACK.
If self-test is enabled then RTACTIVE will be delayed from going active high in accordance with ‘t12’.
t2
CLOCK IN rising to DTREQ low
ALL
ns
t3
DTREQ (low) - to - DTGRT delay time
ALL
s
t4
DTGRT low setup prior to CLOCK IN rising
ALL
ns
t6
CLOCK IN rising to DTACK low
ALL
ns
t7
DTGRT hold time following DTACK falling
ALL
ns
t9
Time for input data to become valid following falling edge of DTACK
t12
RTACTIVE high delayed from DTACK high (see Note 2)
t13
CLOCK IN rising to RTACTIVE high
ALL
ns
REF
DESCRIPTION
CLOCK
FREQUENCY
VALUE @5 VOLTS
UNITS
TABLE FOR FIGURE 12. AUTO-CONFIGURATION - DMA READ TIMING
MIN
TYP
MAX
40
10
40
30
20 MHz
ns
120
16 MHz
ns
157
12 MHz
ns
220
10 MHz
ns
270
20 MHz
ms
1.6
16 MHz
ms
2.0
12 MHz
ms
2.7
10 MHz
ms
3.2
t5
DTGRT falling to DTACK low
20 MHz
ns
100
16 MHz
ns
113
12 MHz
ns
133
10 MHz
ns
150
t8
DTACK low pulse width
20 MHz
185
ns
200
215
16 MHz
235
ns
250
265
12 MHz
318
ns
333
348
10 MHz
385
ns
400
415
VALUE @3.3 VOLTS
MIN
TYP
MAX
40
10
40
30
40
120
157
220
270
1.6
2.0
2.7
3.2
105
118
138
155
185
200
215
235
250
265
318
333
348
385
400
415
t10
Data input hold time following sampling time (see Note 1)
ALL
30
ns
30
t11
CLOCK IN rising to DTREQ, DTACK, and MEMOE high
ALL
ns
30
40
t1
MSTCLR high delay to DTREQ low
20 MHz
35
ns
50
65
16 MHz
47.5
ns
62.5
77.5
12 MHz
68.3
ns
83.3
98.3
10 MHz
85
ns
100
115
35
50
65
47.5
62.5
77.5
68.3
83.3
98.3
85
100
115
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