
NOTES:
Notes 1 through 6 are applicable to the Receiver Differential Resistance
and Differential Capacitance specifications:
(1)
Specifications include both transmitter and receiver (tied together
internally).
(2)
Impedance parameters are specified directly between pins
TX/RX A(B) and
of the SSRT hybrid.
(3)
It is assumed that all power and ground inputs to the hybrid are con-
nected.
(4)
The specifications are applicable for both unpowered and powered
conditions.
(5)
The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6)
Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
(7)
Assumes a common mode voltage within the frequency range of dc
to 2 MHz, applied to the pins of the isolation transformer on the stub
side (either direct or transformer coupled), and referenced to hybrid
ground. Transformer must be a DDC recommended transformer or
other transformer that provides an equivalent minimum CMRR.
(8)
An "X" in one or more of the product type fields indicates that the ref-
erence is applicable to all available product options.
(9)
MIL-STD-1760 requires an output of 20 Vp-p minimum on the stub
connection.
(10) External 10 F tantalum and 0.1 F capacitors to ground should be
located as close as possible to Pins 20 and 72, and a 0.1 F capac-
itor at pin 37.
(11) Power dissipation specifications assume a transformer coupled con-
figuration, with external dissipation (while transmitting) of 0.14 watts
for the active isolation transformer, 0.08 watts for the active bus cou-
pling transformer, 0.45 watts for each of the two bus isolation resis-
tors, and 0.15 watts for each of the two bus termination resistors.
(12) Measured from mid-parity crossing of command word to mid-sync
crossing of RT's status word.
(13) MIL-STD-1760
compliant
output
voltage
not
available
for
BU-61703/5X4 versions.
)
B
(
A
RX
/
TX
INTRODUCTION
GENERAL
The BU-61703/5 Simple System RT (SSRT) is a complete MIL-
STD-1553 Remote Terminal (RT) bus interface unit. Contained in
this hybrid are a dual transceiver and Manchester II
encoder/decoder, and MIL-STD-1553 Remote Terminal (RT) pro-
tocol logic. Also included are built-in self-test capability and a
parallel subsystem interface. The subsystem interface includes a
12-bit address bus and a 16-bit data bus that operates in a 16-
bit DMA handshake transfer configuration. The local bus and
associated control signals may be operated from either +5 volt or
+3.3 volt power.
The transceiver front end of the BU-61703/5 is implemented by
means of low-power monolithic technology. The transceiver
requires only a single +5 V voltage source. The voltage source
transmitters provide superior line driving capability for long
cables and heavy amounts of bus loading. In addition, the mono-
lithic transceivers provide a minimum stub voltage level of 20
volts peak-to-peak transformer coupled, making the BU-61703/5
suitable for MIL-STD-1760 applications.
The receiver sections of the BU-61703/5 are fully compliant with
MIL-STD-1553B in terms of front-end overvoltage protection,
threshold, and bit-error rate.
The BU-61703/5 implements all MIL-STD-1553 message for-
mats, including all 13 MIL-STD 1553 dual redundant mode
codes. Any subset of the possible 1553 commands (broadcast,
T/R bit, subaddress, word count/mode code) may be optionally
illegalized by means of an external PROM, PLD, or RAM. An
extensive amount of message validation is performed for each
message received. Each word received is validated for correct
sync type and sync encoding, Manchester II encoding, parity,
and bit count. All messages are verified to contain a legal,
defined command word and correct word count. If the BU-
61703/5 is the receiving RT in an RT-to-RT transfer, it verifies
that the T/R bit of the transmit command word is logic "1" and
that the transmitting RT responds in time and contains the cor-
rect RT address in its Status Word.
The BU-61703/5 may be operated from a 10, 12, 16, or 20 MHz
clock input. For any clock frequency, the decoder samples
incoming data on both edges of the clock input. This oversam-
pling, in effect, provides for a sampling rate of twice the input
clocks' frequency. Benefits of the higher sampling rate include a
wider tolerance for zero-crossing distortion and improved bit
error rate performance.
The BU-61703/5 includes a hardwired R.T. address input. This
includes 5 address lines, an address parity input, and an
address parity error output. The RT address can also be latched
by means of a latching input signal.
The BU-61703/5 supports command illegalization. Commands
may be illegalized by asserting the input signal
active
low within approximately 2 s after the mid-parity bit zero-cross-
ing of the received command word. Command words may be ille-
ILLEGAL
3
0.6
(17)
1.0 X 1.0 X 0.155
(25.4 x 25.4 x 3.94)
Weight
oz
(g)
in.
(mm)
PHYSICAL CHARACTERISTICS
Size
UNITS
MAX
PARAMETER
TABLE 1. SIMPLE SYSTEM RT SPECIFICATIONS (Cont’d)