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    參數(shù)資料
    型號(hào): BU-61703G3-592K
    廠商: DATA DEVICE CORP
    元件分類: 微控制器/微處理器
    英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
    封裝: CERAMIC, QFP-72
    文件頁數(shù): 5/54頁
    文件大小: 576K
    代理商: BU-61703G3-592K
    13
    Data Device Corporation
    www.ddc-web.com
    BU-61703/61705
    D1 web-09/02-0
    t1
    Mid-parity crossing of received command word delay to
    SA4-SA0, L-BRO, T/R Bit, and WC/MC valid
    ALL
    s
    t2
    Mid-parity crossing of received command word delay to
    falling edge of INCMD
    ALL
    s
    t3
    Mid-parity crossing of received command word delay to
    MSG_ERR and HS_FAIL rising
    ALL
    s
    t4
    ILLEGAL, SRV_RQST, SSFLAG, BUSY input access time from
    SA4-SA0, L-BRO, T/R, and CWC/MC valid
    ALL
    ns
    t5
    RT Sub-Address, L-BRO, and T/R Bit setup time prior to INCMD low
    ALL
    500
    ns
    t6
    ILLEGAL, SRV_RQST, SSFLAG, BUSY valid time following falling
    edge of INCMD
    ALL
    300
    ns
    t7
    Mid-parity crossing to WC/CWC value of 1Fh
    ALL
    s
    t8
    Mid-parity crossing of first data word to DTREQ falling edge
    t9
    WC/CWC data value of 1Fh held
    t10
    CWC valid following falling edge of DTREQ
    ALL
    ns
    t11
    RT Response time.
    ALL
    4
    s
    t12
    Delay from following mid-parity of last received data word to GBR low.
    (see Notes 1, 2)
    ALL
    4
    s
    t13
    Mid-parity crossing of all data words, except first data word, to DTREQ
    falling edge
    ALL
    s
    t14
    GBR pulse width
    20 MHz
    ns
    REF
    DESCRIPTION
    CLOCK
    FREQUENCY
    RESPONSE TIME
    UNITS
    TABLE FOR FIGURE 4. RT RECEIVE COMMAND TIMING (NON-BURST MODE)
    t15
    CWC transition to WC prior to Mid-Sync crossing of Status response.
    MIN
    TYP
    MAX
    1.5
    2
    1.5
    400
    1
    30
    6.5
    7
    1
    100
    16 MHz
    ns
    125
    12 MHz
    ns
    167
    10 MHz
    ns
    200
    t16
    Mid-Sync crossing of status response to RT_FAIL rising
    ALL
    s
    1.5
    t17
    Mid-parity crossing of status word to INCMD rising
    ALL
    s
    3.0
    20 MHz
    s
    1.2
    16 MHz
    s
    1.25
    12 MHz
    s
    1.33
    10 MHz
    s
    1.4
    20 MHz
    ns
    75
    16 MHz
    ns
    94
    12 MHz
    ns
    125
    10 MHz
    ns
    150
    20 MHz
    ns
    200
    16 MHz
    ns
    250
    12 MHz
    ns
    333
    10 MHz
    ns
    400
    NOTES:
    (1)
    Assumes that DTGRT is tied to logic “0”. If DTGRT is not connected
    to logic “0”, the minimum time to drive GBR active low will increase
    by the amount of the DTGRT (low) - to - DTGRT (low) delay.
    (2)
    The transceiver delays are measured at a range of 150ns to 450ns
    for the receiver and 100ns to 250ns for the transmitter.
    相關(guān)PDF資料
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