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參數(shù)資料
| 型號： | BU-61703G3-150L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | CERAMIC, QFP-72 |
| 文件頁數(shù)： | 54/54頁 |
| 文件大?。?/td> | 576K |
| 代理商： | BU-61703G3-150L |
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9
Data Device Corporation
www.ddc-web.com
BU-61703/61705
D1 web-09/02-0
If the protocol self-test fails: (1) the Terminal Flag bit will be set to
logic "1" in the SSRT status word; (2) bit 8 in the SSRT's BIT word,
BIT Test Fail, will be set to logic "1"; (3) the SSRT's RTFAIL output
will be asserted to logic "0".
AUTO-CONFIGURATION
The SSRT includes an auto-configuration feature, which allows
various optional features to be enabled or disabled. Auto-configu-
ration may be enabled or disabled by means of the input signal
AUTO_CFG. If AUTO_CFG is connected to logic "1", then the
auto-configure option is disabled, and the six configuration para-
meters revert to their default values.
Note that the default condition for each configuration para-
meter is enabled (for the MIL-STD-1553A/B protocol selection, -
1553B is the default).
If AUTO_CFG is connected to logic "0", then the configuration
parameters are transferred over D5-D0 by means of a DMA read
data transfer. The transfer occurs during the time that the
RTACTIVE
and DTACK outputs are logic "0", following MSTCLR
transitioning from logic "0" to logic "1" and a successful
DT_REQ-to-DTGRT handshake.
Note that if DTGRT is hardwired to logic "0", the handshake
process is not necessary (i.e., DTACK and RTACTIVE will both
be asserted to logic "0" one clock cycle following DT_REQ).
Each of the configuration parameters is enabled if the SSRT
reads a value of logic "1" for the respective data bit.
The auto-configuration parameters are defined by TABLE 2.
The timing signals pertaining to Auto-Configuration mode are
illustrated in FIGURE 12.
0
1
0
CLK_SEL_0
12 MHz
16 MHz
1
20 MHz
0
10 MHz
0
CLOCK FREQUENCY
CLK_SEL_1
1
TABLE 3. CLOCK FREQUENCY SELECTION
CLOCK INPUT
The SSRT may be operated from one of four clock frequencies:
10, 12, 16, or 20 MHz. The selected clock frequency must be des-
ignated by means of the input signals CLK_SEL_1 and
CLK_SEL_0, as shown in TABLE 3.
MIL-STD-1553A/B
(-B is logic "1", or the
default).
POWER-UP SELF-
TEST ENABLE
BURST MODE
SUBADDRESS 30
WRAPAROUND
RTFAIL-to-TERMINAL
FLAG AUTO-WRAP
RT GOES ONLINE IF
SELF-TEST FAILS
FUNCTION
In MIL-STD-1553B mode, subaddress
31 is a mode code subaddress, and
mode codes are implemented in full
accordance with MIL-STD-1553B. In
MIL-STD-1553A mode, subaddress 31
is a non-mode code subaddress, and no
data words are transmitted or anticipat-
ed to be received for mode code mes-
sages.
If enabled, the SSRT will perform self-
test following the rising edge of MST-
CLR.
0
Enables burst mode (using the internal
FIFO) for received data words. In burst
mode, for a receive message, all data
words are transferred to the external
system in a contiguous burst following
reception of the last data word.
1
Subaddress 30 wraparound is enabled.
That is, the data words for a receive
message to subaddress 30 are stored in
the internal FIFO, and not transferred to
the external system. For a subsequent
transmit message to subaddress 30, the
transmitted data words are read from
the internal FIFO, rather than from the
external system.
2
If the loop test fails for a particular mes-
sage, the Terminal flag bit will be set in
the SSRT's status response for the sub-
sequent non-broadcast message.
4
If logic "0", the RT will become enabled
only if the self-test passes. If auto-config
is not used, or if this bit is logic "1", or if
the power-up self-test passes, then the
RT will go online following self-test.
5
DESCRIPTION
BIT
3
TABLE 2. AUTO-CONFIGURATION PARAMETERS
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