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Data Device Corporation
www.ddc-web.com
BU-61703/61705
D1 web-09/02-0
FIGURE 12. AUTO-CONFIGURATION - DMA READ TRANSFER TIMING
CLOCK IN
DTREQ
DTGRT
DTACK
MEMWR
MEMOE
D15-D0
MSTCLR
RTACTIVE
DATA VALID
t2
t3
t6
t5
t4
t7
t9
t11
t13
note1
t10
t8
t12
AUTO-CONFIGURATION - DMA SINGLE WORD READ
Note1: RTACTIVE asserted high 1 clock following DTACK high assuming self-test is not enabled.
When self-test is enabled RTACTIVE is delayed in the amount of 't12'.
See the table reference for details.
t1