- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄166576 > BU-61703F3-110Q (DATA DEVICE CORP) 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 PDF資料下載
參數(shù)資料
| 型號： | BU-61703F3-110Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | CERAMIC, QFP-72 |
| 文件頁數(shù)： | 51/54頁 |
| 文件大?。?/td> | 576K |
| 代理商： | BU-61703F3-110Q |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁當(dāng)前第51頁第52頁第53頁第54頁
6
Data Device Corporation
www.ddc-web.com
BU-61703/61705
D1 web-09/02-0
down, Override selected transmitter shutdown, and Transmit vec-
tor word mode commands which involve a single data word trans-
fer, the address for the data word is offset from location 0
of the message block for subaddresses 0 and 31 by the value of
the mode code field of the received command word.
The data words transmitted in response to the Transmit last com-
mand or Transmit BIT word mode commands are accessed from
a pair of internal registers.
DMA INTERFACE
A 16-bit data bus, a 12-bit address bus, and six control signals are
provided to facilitate communication with the parallel subsystem.
The data bus D15-D0 consists of bi-directional tri-state signals.
The address bus L_BRO, T/R, SA4-SA0, and WC/MC/CWC4-0;
along with the data transfer control signals MEMOE and MEMWR
are two-state output signals.
The control signals include the standard DMA handshake signals
DTREQ, DTGRT, DTACK, as well as the transfer control outputs
MEMOE and MEMWR. HS_FAIL provides an indication to the
subsystem of a handshake failure condition.
Data transfers between the subsystem and the BU-61703/5 are
performed by means of a DMA handshake, initiated by
the BU-61703/5. A data read operation is defined to be the trans-
fer of data from the subsystem to the BU-61703/5. Conversely, a
data write operation transfers data from the BU-61703/5 to the
subsystem. Data is transferred as a single 16-bit word.
DMA READ OPERATION
In response to a transmit command, the BU-61703/5 needs to
read data words from the external subsystem. To initiate a data
word read transfer, the SSRT asserts the signal DTREQ low.
Assuming that the subsystem asserts DTGRT in time, the SSRT
will then assert the appropriate values of L_BRO (logic "0"), T/R
(high), SA4-0, and MC/CWC4-0; MEMWR high, along with DTACK
low and MEMOE low to enable data to be read from the subsys-
tem.
After the transfer of each Data Word has been completed, the
value of the address bus outputs CWC4 through CWC0 is incre-
mented.
DMA WRITE OPERATION
In response to a receive command, the BU-61703/5 will need to
transfer data to the subsystem. There are two options for doing
this, the burst mode and the non-burst mode. In burst mode, all
received data words are transferred from the SSRT to the subsys-
tem in a contiguous burst, only following the reception of the cor-
rect number of valid data words. In the non-burst mode,
single data words are written to the external subsystem immedi-
ately following the reception of each individual data word.
To initiate a DMA write cycle, the SSRT asserts DTREQ low. The
subsystem must then respond with DTGRT low. Assuming that
DTGRT was asserted in time, the BU-61703/5 will then assert
DTACK low. The BU-61703/5 will then assert the appropriate value
of L_BRO, T/R, SA4-0, and MC/CWC4-0, MEMOE high, and
MEMWR low. MEMWR will be asserted low for one clock cycle.
The subsystem may then use either the falling or rising edge of
MEMWR to latch the data. Similar to the DMA read operation, the
address outputs CWC4 through CWC0 are incremented after the
completion of a DMA write operation.
HANDSHAKE FAIL
Following the assertion of DTREQ low by the SSRT, the external
subsystem has 10 s to respond by asserting DTACK to
logic "0".
If the BU-61703/5 (SSRT) asserts DTREQ and the subsystem
does not respond with DTGRT in time for the BU-61703/5 to com-
plete a data word transfer, the HSFAIL output will be asserted low
to inform the subsystem of the handshake failure, and bit 12 in the
internal Built-In-Test (BIT) word will be set to logic "1". If the hand-
shake failure occurs on a data word read transfer (for a transmit
command), the SSRT will abort the current message transmis-
sion. In the case of a handshake failure on a write transfer
(received command) the SSRT will set the handshake failure out-
put and BIT word bit, and abort processing the current message.
MESSAGE PROCESSING OPERATION
Following the receipt and transfer of a valid Command Word, the
BU-61703/5 will attempt to perform one of the following opera-
tions: (1) transfer received 1553 data to the subsystem, (2) read
data from the subsystem for transmission on the 1553 bus, (3)
transmit status (and possibly the last command word or RT BIT
word) on the 1553 bus, and/or (4) set status word conditions.
The BU-61703/5 responds to all non-broadcast messages to its
RT address with a 1553 Status Word.
RT ADDRESS
RT Address 4-0 (RT_AD_4 = MSB) and RT Address Parity
(RT_AD_P) should be programmed for a unique RT address and
reflect an odd parity sum. The BU-61703/5 will not respond to any
MIL-STD-1553 commands or transfer received data from any non-
broadcast messages if an odd parity sum is not presented by
RT_AD_4-0 and RT_AD_P. An address parity error will be indicat-
ed by a low output on the RT_AD_ERR pin. The input signal
RT_AD_LAT operates a transparent latch for RTAD4-RTAD0 and
RTADP. If RT_AD_LAT is low, the output of the latch tracks the
value presented on the input pins. If RT_AD_LAT is high, the out-
put of the internal latch becomes latched to the values presented
at the time of a low-to-high transition of RT_AD_LAT.
RT address and RT Address Parity must be presented valid
before the mid-parity crossing of the 1553 command and held, at
least, until following the first received data word.
COMMAND ILLEGALIZATION
The BU-61703/5 includes a provision for command illegalization. If
a command is illegalized, the BU-61703/5 will set the Message
error bit and transmit its status word to the Bus Controller. No data
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-61703F3-132K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61703F3-160 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61703F3-170L | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61703G3-140Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61703G3-182K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU-61705 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |Simple System RT |
| BU-61740B3NEW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |μ-ACE (Micro-ACE?) |
| BU-61743 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |Enhanced Mini-ACE? |
| BU-61743F3-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU-61743F3-110 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。