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參數(shù)資料
| 型號： | BU-61588P3-112 |
| 英文描述： | MIL-STD-1553/ARINC Bus Controller/RTU |
| 中文描述： | MIL-STD-1553/ARINC總線控制器/ RTU通訊 |
| 文件頁數(shù)： | 26/32頁 |
| 文件大?。?/td> | 833K |
| 代理商： | BU-61588P3-112 |
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Data Device Corporation
www.ddc-web.com
BU-61559 Series
C-12/02-300
Used to select between the transpar-
ent (when strapped to logic 1) and
buffered (when strapped to logic 0)
modes for the host processor inter-
face.
TRANSPARENT/
BUFFERED
35
50
Strobe Data. Used in conjunction with
SELECT to initiate and control the
data transfer cycle between the host
processor and the BU-61559.
STRBD (I)
34
52
Generally connected to a CPU
address decoder output to select the
BU-61559 for a transfer to/from either
RAM or register. May be tied to
STRBD.
SELECT (I)
74
49
Memory/Register. Generally connected
to either a CPU address line or address
decoder output. Selects between mem-
ory access (MEM/REG = 1) or register
access (MEM/REG = 0).
MEM/REG (I)
33
54
Read/Write. For a host processor
access, selects between reading
(RD/WR = 1) and writing (RD/WR = 0).
RD/WR (I)
36
48
Tri-state control for external address
and data buffers. Generally not need-
ed in the buffered mode. When low,
external buffers should be enabled to
allow the host processor access to the
BUS-61669's RAM and registers.
IOEN (O)
73
51
Handshake output to host processor.
For a read access, signals that data is
available to be read on D15 through
D0. For a write cycle, signals that data
has been transferred to a register or
RAM location.
READYD (O)
75
47
Interrupt request output. If the
LEVEL/PULSE interrupt bit (bit 3) of
Configuration Register #2 is low, a
negative pulse of approximately 500
ns in width is output on INT. If bit 3 is
high, a low level interrupt request out-
put will be asserted on INT.
INT (O)
72
53
SIGNAL NAME
PIN NO.
DESCRIPTION
DIP
FLAT
PROCESSOR INTERFACE (8)
Asserted low during both host proces-
sor and 1553 protocol/memory man-
agement memory transfer cycles. Used
as a memory chip select (CS) signal for
external RAM in the transparent mode.
MEMENA-OUT
(O)
31
58
Chip Select (CS) input to 8K X 16 of
internal shared RAM. If only internal
RAM is used (always the case in the
buffered mode), connect directly to
MEMENA-OUT.
MEMENA-IN (I)
69
59
Memory Output Enable/Address Latch.
In transparent mode, output used to
enable data outputs for external RAM
read cycles. In buffered mode, input
used to configure the internal address
buffers in latched mode (when low) or
transparent mode (when high).
MEMOE (O)/
ADDR_LAT (I),
30
60
Memory Write. Asserted low during
memory write transfers to strobe data
into internal or external RAM. Used in
transparent mode.
MEMWR (O)
68
61
SIGNAL NAME
PIN NO.
DESCRIPTION
DIP
FLAT
MEMORY INTERFACE AND ADDRESS
LATCH CONTROL (4)
Analog Transmit/Receive Input/Outputs.
Connect directly to 1553 isolation trans-
formers.
TX/RX-A (I/O)
40
40
TX/RX-A (I/O)
78
41
TX/RX-B (I/O)
20
39
TX/RX-B (I/O)
59
38
SIGNAL NAME
PIN NO.
DESCRIPTION
DIP
FLAT
1553 ISOLATION TRANSFORMER INTERFACE (4)
Remote Terminal Address Inputs
Remote Terminal Address Parity. Must
provide odd parity sum with RTAD4-
RTAD0 in order for the RT to respond to
non-broadcast commands.
RTAD4 (MSB) (I)
11
21
RTAD3 (I)
49
18
RTAD2 (I)
50
20
RTAD1 (I)
9
17
RTAD0 (MSB) (I)
RTAD (I)
10
51
19
22
SIGNAL NAME
PIN NO.
DESCRIPTION
DIP
FLAT
RT ADDRESS (6)
TABLE 7. SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT)
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