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| 型號(hào)： | BU-61586S0-150Z |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| 封裝： | 1.900 X 1 INCH, 0.165 INCH HEIGHT, LOW PROFILE, CERAMIC, DIP-70 |
| 文件頁(yè)數(shù)： | 26/44頁(yè) |
| 文件大?。?/td> | 298K |
| 代理商： | BU-61586S0-150Z |
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32
FIGURE 17. ADDRESS LATCH TIMING
SELECT
MSB/LSB
MEM/REG
(1)
(2)
(3)
(4)
(5)
(1)
(2)
(3)
(4)
t4
t5
A15-A0
ADDR_LAT
SELECT
MSB/LSB
MEM/REG
A15-A0
INPUT
SIGNALS
INTERNAL
VALUES
t1
t3
t2
TABLE FOR FIGURE 17. ADDRESS LATCH TIMING
REF
DESCRIPTION
MIN
TYP
MAX
UNITS
t1
ADDR_LAT pulse width
20
ns
t2
ADDR_LAT high delay to internal signals valid
10
ns
t3
Propagation delay from external input signals to internal signals valid
10
ns
t5
t4
Input hold time following falling edge of ADDR_LAT
Input setup time prior to falling edge of ADDR_LAT
20
10
ns
Notes for FIGURE 17 and associated table.
1. Applicable to buffered mode only. Address SELECT AND MEM/REG latches are always transparent in the transparent mode of operation.
2. Latches are transparent when ADDR_LAT is high. Internal values do not update when ADDR_LAT is low.
3. MSB/LSB input signal is applicable to 8-bit mode only (16/8 input = logic “0”). MSB/LSB input is a “don’t care” for 16-bit operation.
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