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      參數(shù)資料
      

      


      


      
型號(hào)：
BU-61585V3-300Y

      

      
廠商：
DATA DEVICE CORP

      

      
元件分類：
微控制器/微處理器

      

      
英文描述：
2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70

      

      
封裝：
48.30 X 25.40 MM, 3.81 MM HEIGHT, FP-70

      

      
文件頁數(shù)：
10/44頁

      

      
文件大小：
563K

      

      
代理商：
BU-61585V3-300Y


      

      

      

	
      
    
    

    
      
	
      18
      Data Device Corporation
      www.ddc-web.com
      BU-65170/61580/61585
      H1 web-09/02-0
      Error bit in its internal Status Register, regardless of whether
      or not corresponding bit in the illegalization RAM has been
      set. If the next message is a Transmit Status or Transmit Last
      Command mode code, the ACE will respond with its
      Message Error bit set.
      PROGRAMMABLE BUSY
      As a means of providing compliance with Notice 2 of MIL-STD-
      1553B, the BU-65170/61580 RT provides a software controllable
      means for setting the Busy Status Word bit as a function of sub-
      address. By a Busy Lookup Table in the BU-65170/61580
      address space, it is possible to set the Busy bit based on com-
      mand broadcast/own address, T/R bit, and subaddress. Another
      programmable option, allows received Data Words to be either
      stored or not stored for messages, when the Busy bit is set.
      OTHER RT FUNCTIONS
      The BU-65170/61580 allows the hardwired RT Address to be
      read by the host processor. Also, there are options for the RT
      FLAG Status Word bit to be set under software control and/or
      automatically following a failure of the loopback self-test. Other
      software controllable RT options include software programmable
      RT Status and RT BIT words, automatic clearing of the Service
      Request Status Word bit following a Transmit Vector Word mode
      command, capabilities to clear and/or load the Time Tag Register
      following receipt of Synchronize mode commands, options
      regarding Data Word transfers for the Busy and/or Message
      Error (Illegal) Status Word bits, and for handling of 1553A and
      reserved mode codes.
      MONITOR (MT) ARCHITECTURE
      The BU-61580 provides three bus monitor (MT) modes:
      (1) The “AIM-HY” (default) or “AIM-HY'er” Word Monitor mode.
      (2) A Selective Message Monitor mode.
      (3) A Simultaneous Remote Terminal/Selective Message Monitor
      mode.
      The strong recommendation for new applications is the use of
      the Selective Message Monitor, rather than the Word Monitor.
      Besides providing monitor filtering based on RT Address, T/R bit,
      and Subaddress, the Message Monitor eliminates the need to
      determine the start and end of messages by software. The devel-
      opment of such software tends to be a tedious task. Moreover, at
      run time, it tends to entail a high degree of CPU overhead.
      WORD MONITOR
      In the Word Monitor mode, the BU-61580 monitors both 1553
      buses. After initializing the Word Monitor and putting it on-line the
      BU-61580 stores all Command, Status, and Data Words
      received from both buses. For each word received from either
      bus, the BU-61580 stores a pair of words in RAM. The first word
      is the 16 bits of data from the received word. The second word is
      the Monitor Identification (ID), or “Tag” word. The ID Word con-
      tains information relating to bus channel, sync type, word validi-
      ty, and interword time gaps. The BU-61580 stores data and ID
      words in a circular buffer in the shared RAM address space.
      TABLE 23 shows the bit mapping for the Monitor ID word.
      MONITOR TRIGGER WORD
      There is a Trigger Word Register that provides additional flexibil-
      ity for the Word Monitor mode. The BU-61580 stores the value of
      the 16-bit Trigger Word in the MT Trigger Word Register. The con-
      tents of this register represent the value of the Trigger Command
      Word. The BU-61580 has programmable options to start or stop
      the Word Monitor, and/or to issue an interrupt request following
      receipt of the Trigger Command Word from the 1553 bus.
      SELECTIVE MESSAGE MONITOR MODE
      The BU-61580 Selective Message Monitor provides features to
      greatly reduce the software and processing burden of the host
      CPU. The Selective Message Monitor implements selective mon-
      itoring of messages from a dual 1553 bus, with the monitor fil-
      tering based on the RT Address, T/R bit, and Subaddress fields
      of received 1553 Command Words. The Selective Message
      Monitor mode greatly simplifies the host processor software by
      distinguishing between Command and Status Words. The
      Selective Message Monitor maintains two stacks in the BU-
      61580 RAM: a Command Stack and a Data Stack.
      Simultaneous RT/Message Monitor Mode
      The Selective Message Monitor may function as a purely passive
      monitor or may be programmed to function as a simultaneous
      RT/Monitor. The RT/Monitor mode provides complete Remote
      Terminal (RT) operation for the BU-61580's strapped RT address
      and bus monitor capability for the other 30 nonbroadcast RT
      addresses. This allows the BU-61580 to simultaneously operate
      as a full function RT and “snoop” on all or a subset of the bus
      activity involving the other RTs on a bus. This type of operation
      is sometimes needed to implement a backup bus controller. The
      combined RT/Selective Monitor maintains three stack areas in
      the BU-61580 address space: an RT Command Stack, a Monitor
      Command Stack, and a Monitor Data Stack. The pointers for the
      various stacks have fixed locations in the BU-61580 address
      space.
      WC4/MC4
      0(LSB)
      SA0
      1
      SA1
      2
      0
      SA2
      3
      SA3
      4
      SA4
      5
      T/R
      6
      BROADCAST/OWN_ADDRESS
      7
      1
      8
      1
      9
      0
      10
      0
      12
      0
      13
      0
      14
      0
      15(MSB)
      DESCRIPTION
      BIT
      11
      TABLE 29. ILLEGALIZATION RAM ADDRESS DEFINITION
      
    
      
    
    
      


      


      

      相關(guān)PDF資料
      		

      PDF描述
      		

      
      

      
BU-61585V3-452K
2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70

      

      
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