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| 型號(hào)： | BU-61585S3-820W |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| 封裝： | 48.30 X 25.40 MM, 4.19 MM HEIGHT, DIP-70 |
| 文件頁(yè)數(shù)： | 34/44頁(yè) |
| 文件大?。?/td> | 563K |
| 代理商： | BU-61585S3-820W |
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4
Data Device Corporation
www.ddc-web.com
BU-65170/61580/61585
H1 web-09/02-0
INTRODUCTION
DDC's ACE series of Integrated BC/RT/MT hybrids provide a
complete, flexible interface between a microprocessor and a
MIL-STD-1553A, B Notice 2, McAir, or STANAG 3838 bus,
implementing Bus Controller, Remote Terminal (RT) and Monitor
Terminal (MT) modes. Packaged in a single 1.9-square-inch,
70-pin DIP or surface mountable flatpack or J-lead package, the
ACE
series
contains
dual
low-power
transceivers
and
encoder/decoders, complete BC/RT/MT multi-protocol logic,
memory management and interrupt logic, 4K x 16 of shared sta-
tic RAM and a direct, buffered interface to a host processor bus.
The BU-65170/61580 contains internal address latches and bidi-
rectional data buffers to provide a direct interface to a host
processor bus. The BU-65170/61580 may be interfaced directly
to both 16-bit and 8-bit microprocessors in a buffered shared
RAM configuration. In addition, the ACE may connect to a 16-bit
processor bus via a Direct Memory Access (DMA) interface. The
BU-65170/61580 includes 4K words of buffered RAM.
Alternatively, the ACE may be interfaced to as much as 64K
words of external RAM in either the shared RAM or DMA config-
urations.
The ACE RT mode is multiprotocol, supporting MIL-STD-1553A,
MIL-STD-1553B Notice 2, STANAG 3838 (including EFAbus),
and the McAir A3818, A5232, and A5690 protocols. Full compli-
ance to the McAir specs, however, requires the use of a sinu-
soidal transceiver (transceiver option 5). Refer to the BU-61590
data sheet for additional information on McAir terminals.
The memory management scheme for RT mode provides an
option for separation of broadcast data, in compliance with
1553B Notice 2. Both double buffer and circular buffer options
are programmable by subaddress. These features serve to
ensure data consistency and to off-load the host processor for
bulk data transfer applications.
The ACE series implements three monitor modes: a word moni-
tor, a selective message monitor, and a combined RT/selective
monitor. Other features include options for automatic retries and
programmable intermessage gap for BC mode, an internal Time
Tag Register, an Interrupt Status Register and internal command
illegalization for RT mode.
FUNCTIONAL OVERVIEW
TRANSCEIVERS
The transceivers in the BU-65170/61580X3(X6) are fully mono-
lithic, requiring only a +5 volt power input. Besides eliminating
the need for an additional power supply, the use of a 5 volt (only)
transceiver requires the use of step-up, rather than step-down,
isolation transformers. This provides the advantage of a higher
terminal input impedance than is possible for a 15 volt or 12 volt
transmitter. As a result, there is greater margin for the input
impedance test, mandated for 1553 validation testing. This
allows for longer cable lengths between an LRU's system con-
nector and the isolation transformers of an embedded 1553 ter-
minal.
For the +5 V and -15 V/-12 V front end, the BU-65170/
61580X1(X2) uses low-power bipolar analog monolithic and
thick-film hybrid technology. The transceiver requires +5 V and -
15 V (-12 V) only (requiring no +15 V/+12 V) and includes volt-
age source transmitters. The voltage source transmitters provide
superior line driving capability for long cables and heavy
amounts of bus loading. In addition, the monolithic transceivers
in the BU-65170/61580X1 provide a minimum stub voltage level
of 20 volts peak-to-peak transformer coupled, making them suit-
able for MIL-STD-1760 applications.
The receiver sections of the BU-65170/61580 are fully compliant
with MIL-STD-1553B in terms of front end overvoltage protec-
tion, threshold, common mode rejection, and word error rate. In
addition, the receiver filters have been designed for optimal oper-
ation with the J chip's Manchester II decoders.
J DIGITAL MONOLITHIC
The J digital monolithic represents the cornerstone element of
the ACE family of terminals. The development of the J chip rep-
resents the fifth generation of 1553 protocol and interface design
for DDC. Over the years, DDC's 1553 protocol and interface
design has evolved from: (1) discrete component sets, consisting
of multiple hybrids (with large numbers of chips inside the indi-
vidual hybrids) and programmable logic devices, to (2) multiple
custom ASICs to perform the functions of encoder/decoder and
RT protocol within a single hybrid, to (3) the BUS-61553
Advanced Integrated Mux Hybrid (AIM-HY) series, containing, in
addition to a dual monolithic/thick-film transceiver and discrete
RAM chips, a custom protocol chip and a separate custom mem-
ory management/processor interface chip, to (4) the BUS-61559
Advanced Integrated Mux Hybrids with Enhanced RT Features
(AIM-HY'er — the AIM-HY'er series includes memory manage-
ment and processor interface functions beyond those of the AIM-
HY series) , to (5) the full integration of the J chip.
Notes for Table 1: Notes 1 through 6 are applicable to the Receiver
Differential Resistance and Differential Capacitance specifications:
(1) Specifications include both transmitter and receiver (tied together
internally).
(2) Measurement of impedance is directly between pins TX/RX A(B)
and TX/RX A(B) of the BU-65170/61580XX hybrid.
(3) Assuming the connection of all power and ground inputs to the
hybrid.
(4) The specifications are applicable for both unpowered and powered
conditions.
(5) The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6) Minimum resistance and maximum capacitance parameters are
guaranteed,but not tested, over the operating range.
(7) Assumes a common mode voltage within the frequency range of dc
to 2MHz, applied to pins of the isolation transformer on the stub
side (either direct or transformer coupled), referenced to hybrid
ground. Use a DDC recommended transformer or other transformer
that provides an equivalent minimum CMRR.
(8) Typical value for minimum intermessage gap time. Under software
control, may be lengthened to (65,535s minus message time), in
increments of 1s.
(9) Software programmable (4 options). Includes RT-to-RT Timeout
(Mid-Parity of Transmit Command to Mid-Sync of Transmitting RT
Status).
(10) For both +5V logic and transceiver. +5V for channels A and B.
(11) Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
(12) Specifications for BU-65171, BU-61581, and BU-61586 are identi-
cal to the specifications for the BU-65170, BU-61580, and BU-
61585 respectively.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU-61586 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |ACE |
| BU61586V6-300 | 制造商:DDC 功能描述:MIL-STD-1553/ARINC BUS CONTROLLER/RTU, 70 Pin, Flat Pack |
| BU-61588 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MINIATURE ADVANCED COMMUNICATION ENGINE (MINI-ACE) AND MINI-ACE PLUS |
| BU-61588F0 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MINIATURE ADVANCED COMMUNICATION ENGINE (MINI-ACE) AND MINI-ACE PLUS |
| BU-61588F3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MINIATURE ADVANCED COMMUNICATION ENGINE (MINI-ACE) AND MINI-ACE PLUS |
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