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| 型號(hào)： | BU-61585S3-190L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| 封裝： | 48.30 X 25.40 MM, 4.19 MM HEIGHT, DIP-70 |
| 文件頁(yè)數(shù)： | 14/44頁(yè) |
| 文件大小： | 563K |
| 代理商： | BU-61585S3-190L |
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21
Data Device Corporation
www.ddc-web.com
BU-65170/61580/61585
H1 web-09/02-0
READYD low indicates to the host processor that read data is
available on the parallel data bus, or that write data has been
stored. At this time, the CPU should bring the signal STRBD
high, completing the transfer cycle.
Address Latch Timing
FIGURE 17 illustrates the operation and timing of the address
input latches for the buffered interface mode. In the transparent
mode, the address buffers are always transparent. Since the
transparent mode requires the use of external buffers, external
address latches would be required to demultiplex a multiplexed
address bus. In the buffered mode, however, the ACE's internal
address latches may be used to perform the demultiplexing func-
tion.
The ADDR_LAT input signal controls address latch operation.
When ADDR_LAT is high, the outputs of the latch (which drive
the ACE's internal memory bus) track the state of address inputs
A15 – A00. When it is low, the internal memory bus remains
latched at the state of A15 – A00 just prior to the falling edge of
ADDR_LAT.
MISCELLANEOUS
SELF-TEST
The BU-65170/61580 products incorporate several self-test fea-
tures. These features include an on-line wraparound self-test for
all messages in BC and RT modes, an off-line wraparound self-
test for BC mode, and several other internal self-test features.
The BC/RT on-line loop test involves a wraparound test of the
encoder/decoder and transceiver. The BC off-line self-test
involves the encoder/decoder, but not the transceiver. These
tests entail checking the received version of every transmitted
word for validity (sync, encoding, bit count, parity) and checking
the received version of the last transmitted word for a bit-by-bit
comparison with the encoded word. The loopback test also fails
if there is a timeout of the internal transmitter watchdog timer.
Note that the timeout value of the watchdog timer depends on
the mode of operation selected (1553A or 1553B). A failure of the
loop test results in setting a bit in the message's Block Status
Word and, if enabled, will result in an interrupt request. With
appropriate host processor software, the BC off-line test is able
to exercise the parallel and serial data paths, encoder, decoder,
and a substantial portion of the BC protocol and memory man-
agement logic.
There are additional built-in self-test features, that involve the
use of three configuration register bits and the eight test regis-
ters. This allows a test of approximately 99% of the J’ chip's inter-
nal logic. These tests include an encoder test, a decoder test, a
register test, a protocol test, and a test of the fail-safe (transmit-
ter timeout) timer.
There is also a test mode. In the test mode, the host processor
can emulate arbitrary activity on the 1553 buses by writing to a
pair of test registers. The test mode can be operated in conjunc-
tion with the Word Monitor mode to facilitate end-to-end self-
tests.
RAM PARITY GENERATION AND CHECKING
The architecture of the J’ monolithic is such that the amount of
buffered RAM may be extended beyond the 4K words of on-chip
J’ RAM. For this off-chip buffered RAM, the J’ chip includes pro-
visions to implement parity generation and checking. Parity gen-
eration and checking provides a mechanism for checking the
data integrity of the internal, buffered memory. Furthermore, 17-
bit, rather than 16-bit, wide buffered RAM would be used. For this
RAM, the J’ chip will generate the 17th bit (parity bit) for all (host
and 1553) write accesses and check the parity bit for all read
accesses. If a parity error occurs, an interrupt request may be
issued, and the corresponding bit in the Interrupt Status Register
would be set. The BU-61585 incorporates an additional 8K x 17
RAM chip.
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