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      • 參數(shù)資料
        型號(hào): BU-61585G6-430W
        廠商: DATA DEVICE CORP
        元件分類: 微控制器/微處理器
        英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
        封裝: GULLWING PACKAGE-70
        文件頁數(shù): 6/44頁
        文件大小: 563K
        代理商: BU-61585G6-430W
        14
        Data Device Corporation
        www.ddc-web.com
        BU-65170/61580/61585
        H1 web-09/02-0
        include a set of interrupt conditions, internal command illegaliza-
        tion, and programmable busy by subaddress.
        RT MEMORY ORGANIZATION
        TABLE 26 illustrates a typical memory map for the BU-61580 in
        RT mode. As in BC mode, the two Stack Pointers reside in fixed
        locations in the shared RAM address space: address 0100 (hex)
        for the Area A Stack Pointer and address 0104 for the Area B
        Stack Pointer. Besides the Stack Pointer, for RT mode there are
        several other areas of the ACE address space designated as
        fixed locations. All RT modes of operation require the Area A and
        Area B Lookup Tables. Also allocated are several fixed locations
        for optional features: Command Illegalization Lookup Table,
        Mode Code Selective Interrupt Table, Mode Code Data Table,
        and Busy Bit Lookup Table. It should be noted that any unen-
        abled optional fixed locations may be used for general purpose
        storage (data blocks).
        The RT Lookup tables, which provide a mechanism for mapping
        data blocks for individual Tx/Rx/Bcst-subaddresses to areas in
        the RAM, occupy address range locations are 0140 to 01BF for
        Area A and 01C0 to 023F for Area B. The RT lookup tables
        include Subaddress Control Words and the individual Data Block
        Pointers. If used, address range 0300-03FF will be dedicated as
        the illegalizing section of RAM. The actual Stack RAM area and
        the individual data blocks may be located in any of the nonfixed
        areas in the shared RAM address space.
        RT MEMORY MANAGEMENT
        One of the salient features of the ACE series products is the flex-
        ibility of its RT memory management architecture. The RT archi-
        tecture allows the memory management scheme for each trans-
        mit, receive, or broadcast subaddress to be programmable on a
        subaddress basis. Also, in compliance with MIL-STD-1553B
        Notice 2, the BU-65170/61580 provides an option to separate
        data received from broadcast messages from nonbroadcast
        received data.
        Besides supporting a global double buffering scheme (as in BC
        mode), the ACE RT provides a pair of 128-word Lookup Tables
        for memory management control. They are programmable on a
        subaddress basis (refer to TABLE 27). These 128-word tables
        include 32-word tables for transmit message pointers and
        receive message pointers. There is also a third, optional Lookup
        Table for broadcast message pointers, providing Notice 2 com-
        pliance, if necessary.
        The fourth section of each of the RT Lookup Tables stores the 32
        Subaddress Control Words (refer to TABLE 9 and 28). The indi-
        vidual Subaddress Control Words may be used to select the RT
        memory management option and interrupt scheme for each
        transmit, receive, and (optionally) broadcast subaddress.
        For each transmit subaddress, there are two possible memory
        management schemes: (1) single message; and (2) circular
        buffer. For each receive (and optionally broadcast) subaddress,
        there are three possible memory management schemes: (1) sin-
        gle message; (2) double buffered; and (3) circular buffer. For
        each transmit, receive and broadcast subaddress, there are two
        interrupt conditions that are programmable by the respective
        Subaddress Control Word: (1) after every message to the sub-
        Data Block 100
        0FE0-0FFF
        Data Block 6
        0420-043F
        Data Block 5
        0400-041F
        Command Illegalizing Table (fixed area)
        0300-03FF
        RESERVED
        Data Block 1-4
        0280-02FF
        Data Block 0
        0260-027F
        (not used)
        0248-025F
        Busy Bit Lookup Table (fixed area)
        0240-0247
        Lookup Table B (fixed area)
        01C0-023F
        Lookup Table A (fixed area)
        0140-01BF
        Mode Code Data (fixed area)
        0110-013F
        Mode Code Selective Interrupt Table (fixed area)
        0108-010F
        Stack Pointer B (fixed location)
        0104
        RESERVED
        0101-0103
        Stack Pointer A (fixed location)
        0100
        Stack A
        0000-00FF
        DESCRIPTION
        ADDRESS
        (HEX)
        0105-0107
        TABLE 26. TYPICAL RT MEMORY MAP (SHOWN FOR 4K RAM)
        TABLE 27. LOOK-UP TABLES
        AREA A
        AREA B
        DESCRIPTION
        COMMENT
        01C0
        .
        01DF
        Rx(/Bcst)_SA0
        .
        Rx(/Bcst)_SA31
        Receive
        (/Broadcast)
        Lookup Table
        01E0
        .
        01FF
        Tx_SA0
        .
        Tx_SA31
        Transmit
        Lookup Table
        0200
        .
        021F
        Bcst_SA0
        .
        Bcst_SA31
        Broadcast
        Lookup Table
        Optional
        0220
        .
        023F
        SACW_SA0
        .
        SACW_SA31
        Subaddress
        Control Word
        Lookup Table
        (Optional)
        0140
        .
        015F
        0160
        .
        017F
        0180
        .
        019F
        01A0
        .
        01BF
        MM2
        MM1
        MM0
        COMMENT
        0
        Single Message or Double Buffered
        0
        1
        128-Word
        0
        1
        0
        256-Word
        0
        1
        512-Word
        1
        0
        1
        0
        1
        0
        8192-Word
        4096-Word
        2048-Word
        1024-Word
        Circular Buffer of
        Specified Size
        DESCRIPTION
        TABLE 28. SUBADDRESS CONTROL WORD
        Memory Management Subaddress Buffer Scheme
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