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參數(shù)資料
| 型號： | BU-61583G1-120L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| 封裝： | CERAMIC, GULL LEAD, 70 PIN |
| 文件頁數(shù)： | 35/48頁 |
| 文件大?。?/td> | 378K |
| 代理商： | BU-61583G1-120L |
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40
Data Device Corporation
www.ddc-web.com
BU-61582
G-08/02-250
External Time Tag Clock input. Use may be designated by bits 7, 8, and 9 of Configuration Register #2. When used it
increments the internal Time Tag Register/Counter. If not used, should be connected to +5V or ground.
63
TAG_CLK (I)
Subsystem Flag or External Trigger input. In the Remote Terminal mode, asserting this input, will set the Subsystem Flag
bit in the BU-61582’s RT Status Word. A low on the SSFLAG input overrides a logic “1” of the respective bit (bit 8) of
Configuration Register #1. In the Bus Controller mode, an enabled external BC Start option (bit 7 of Configuration
Register #1) and a low-to-high transition on this input will issue a BC Start command, starting execution of the current
BC frame. In the Word Monitor mode, an enabled external trigger (bit 7 of Configuration Register #1) and a low-to-high
transition on this input will issue a monitor trigger.
27
SSFLAG (I)/
EXT_TRIG (I)
In Command. In BC mode, asserted low throughout processing cycle for each message. In RT mode or Message
Monitor mode, asserted low following receipt of Command Word and kept low until completion of current message
sequence. In Word Monitor mode, goes low following MONITOR START command, kept low while monitor is on-line,
goes high following RESET command.
45
INCMD (O)
Master Clear. Negative true Reset input, normally asserted low following power turn-on. Requires a minimum 100ns neg-
ative pulse to reset all internal logic to its “power turn-on” state.
7
MSTCLR (I)
16MHz (or 12MHz) clock input.
19
CLOCK IN (I)
DESCRIPTION
PIN
SIGNAL NAME
SIGNAL DESCRIPTIONS, POWER AND GROUND (8)
-VB
CH. B Transceiver Ground
37
-
GNDB
CH. B +5V Supply
38
-
CH. B -15V(-12V) Supply
36
-
+5VB
CH. A Transceiver Ground
69
-
GNDA
CH. A +5V Supply
68
-
+5VA
CH. A -15V(-12V) Supply
70
-
-VA
Logic Ground
18
LOGIC GND
Logic +5V Supply
54
+5V LOGIC
DESCRIPTION
X1/X2*
X0*
PIN
SIGNAL NAME
SIGNAL DESCRIPTIONS, RT ADDRESS (6)
RTADP (I)
Remote Terminal Address Parity. Must provide odd parity sum with RTAD4-RTAD0 in order for the RT to respond to non-
broadcast commands.
44
39
RTAD0 (LSB) (I)
40
RTAD1 (I)
Remote Terminal Address Inputs
41
RTAD2 (I)
42
RTAD3 (I)
43
RTAD4 (MSB) (I)
DESCRIPTION
PIN
SIGNAL NAME
SIGNAL DESCRIPTIONS, MISCELLANEOUS (5)
Note: *Pin X0, X1/X2, X3, X6 refer to package option(X) and Voltage Transceiver option (0, 1, 2, 3, 6). See ordering information.
For X1/X2 versions logic GND, GNDA + GNDB are internally connected.
37
38
-
69
68
-
18
54
X6*
X3*
PIN
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