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參數(shù)資料
| 型號： | BU-61583D3-191 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| 封裝： | CERAMIC, DIP-70 |
| 文件頁數(shù)： | 37/48頁 |
| 文件大?。?/td> | 378K |
| 代理商： | BU-61583D3-191 |
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Data Device Corporation
www.ddc-web.com
BU-61582
G-08/02-250
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TX_INH_B_IN
Transmitter inhibit inputs for the Channel A and Channel B MIL-STD-1553 transmitters. For normal
operation, these inputs should be connected to logic "0". To force a shutdown of Channel A and/or
Channel B, a value of logic "1" should be applied to the respective TX_INH input.
Digital manchester biphase receive data inputs. Connect directly to corresponding outputs of a MIL-
STD-1553 or MIL-STD-1773 transceiver.
-
TX_INH_A_IN
-
34
35
RXB
Digital manchester biphase transmit data outputs. Connect directly to corresponding inputs to a MIL-
STD-1553 or MIL-STD-1773 (fiber optic) transceiver.
-
2
-
37
-
69
RXA
TXB
TXA
-
1
-
38
-
70
RXA
TXB
TXA
DESCRIPTION
X1/X2
PIN
X0
PIN
SIGNAL NAME
Note: *Pin X0, X1/X2, X3, X6 refer to package option(X) and Voltage Transceiver option (0, 1, 2, 3, 6). See ordering information.
-
X3
PIN
36
70
-
X6
PIN
-
N/C
No User Connections
-
N/C
70
36
-
16-bit bidirectional data bus. This bus interfaces the host processor to the internal registers and 16K words of RAM. In
addition, in the transparent mode, this bus allows data transfers to take place between the internal protocol/memory man-
agement logic and up to 64K x 16 of external RAM. Most of the time, the outputs for D15 through D0 are in their high
impedance state. They drive outward in the buffered or transparent mode when the host CPU reads the internal RAM or
registers. Or, in the transparent mode, when the protocol/memory management logic is accessing (either reading or writ-
ing) internal RAM or writing to external RAM.
46
D10
D00
47
D01
48
D02
49
D03
D04
50
51
D05
52
D06
53
D07
55
D08
56
57
D09
58
D11
59
D12
SIGNAL DESCRIPTIONS, DATA BUS (16)
60
D13
61
D14
62
D15 (MSB)
DESCRIPTION
PIN
SIGNAL NAME
SIGNAL DESCRIPTIONS, TRANSMITTER/RECEIVERS (14)
-
36
TX_INH_B_OUT
Digital Transmit Inhibit outputs. Connect to TX_INH_OUT inputs of a MIL-STD-1553 transceiver.
Asserted high to inhibit when not transmitting on the respective bus.
-
68
TX_INH_A_OUT
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相關(guān)PDF資料 |
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| BU-61583D3-200Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61583D3-201W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61583D3-201 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61583D3-290Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61583D3-290W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
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