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參數(shù)資料
| 型號： | BU-61582G1-800 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| 封裝： | CERAMIC, GULL LEAD, 70 PIN |
| 文件頁數(shù)： | 46/48頁 |
| 文件大?。?/td> | 378K |
| 代理商： | BU-61582G1-800 |
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7
Data Device Corporation
www.ddc-web.com
BU-61582
G-08/02-250
ADDRESSING, INTERNAL REGISTERS, AND MEMORY
MANAGEMENT
The software interface of the BU-61582 to the host processor
consists of 17 internal operational registers for normal operation,
an additional 8 test registers, plus 64K X 16 of shared memory
address space. The BU-61582’s 16K X 16 of internal RAM
resides in this address space. Reference TABLE 4.
Definition of the address mapping and accessibility for the
SP’ACE’s 17 nontest registers, and the test registers, is as fol-
lows:
Interrupt Mask Register:
Used to enable and disable interrupt requests for various condi-
tions.
Configuration Registers #1 and #2:
Used to select the BU-61582’s mode of operation, and for soft-
ware control of RT Status Word bits, Active Memory Area, BC
Stop-on-Error, RT Memory Management mode selection, and
control of the Time Tag operation.
Start/Reset Register:
Used for “command” type functions, such as software reset,
BC/MT Start, Interrupt Reset, Time Tag Reset, and Time Tag
Register Test. The Start/Reset Register includes provisions for
stopping the BC in its auto-repeat mode, either at the end of the
current message or at the end of the current BC frame.
BC/RT Command Stack Pointer Register:
Allows the host CPU to determine the pointer location for the cur-
rent or most recent message when the BU-61582 is in BC or RT
modes.
BC Control Word/RT Subaddress Control Word
Register:
In BC mode, allows host access to the current or most recent BC
Control Word. The BC Control Word contains bits that select the
active bus and message format, enable off-line self-test, mask-
ing of Status Word bits, enable retries and interrupts, and speci-
fy MIL-STD-1553A or -1553B error handling. In RT mode, this
register allows host access to the current or most recent
Subaddress Control Word. The Subaddress Control Word is
used to select the memory management scheme and enable
interrupts for the current message. The read/write accessibility
can be used as an aid for testing the SP’ACE hybrid.
Time Tag Register:
Maintains the value of a real-time clock. The resolution of this
register is programmable from among 2, 4, 8, 16, 32, and 64
s/LSB. The TAG_CLK input signal also may cause an external
reserved
1
1F
reserved
0
1
18
Test Mode Register 7
1
0
1
17
Test Mode Register 0
0
1
10
RT BIT Word Register (RD)
1
0
0F
RT Status Word Register (RD)
0
1
0
0E
BC Frame Time/RT Last Command
/MT Trigger Word Register (RD/WR)
1
0
1
0
0D
BC Time Remaining to Next Message
Register (RD/WR)
0
1
0
0C
BC Frame Time Remaining Register
(RD/WR)
1
0
1
0
0B
Data Stack Address Register (RD/WR)
0
1
0
1
0
0A
Configuration Register #5 (RD/WR)
1
0
1
0
09
Configuration Register #4 (RD/WR)
0
1
0
08
Configuration Register #3 (RD/WR)
1
0
07
Interrupt Status Register (RD)
0
1
0
06
Time Tag Register (RD/WR)
1
0
1
0
05
BC Control Word/RT Subaddress Control
Word Register (RD/WR)
0
1
0
04
BC/RT Command Stack Pointer Register
(RD)
1
0
03
Start/Reset Register (WR)
1
0
03
Configuration Register #2 (RD/WR)
0
1
0
02
Configuration Register #1 (RD/WR)
1
0
01
Interrupt Mask Register (RD/WR)
0
00
A0
A1
A2
A3
A4
HEX
REGISTER
DESCRIPTION/ACCESSIBILITY
ADDRESS LINES
TABLE 4. ADDRESS MAPPING
oscillator to clock the Time Tag Register. Start-of-Message
(SOM) and End-of-Message (EOM) sequences in BC, RT, and
Message Monitor modes cause a write of the current value of
the Time Tag Register to the stack area of RAM.
Interrupt Status Register:
Mirrors the Interrupt Mask Register and contains a Master
Interrupt bit. It allows the host processor to determine the cause
of an interrupt request by means of a single READ operation.
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