- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄256244 > BU-61582F1-141Q (DATA DEVICE CORP) 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 PDF資料下載
參數(shù)資料
| 型號(hào)： | BU-61582F1-141Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| 封裝： | CERAMIC, DFP-70 |
| 文件頁數(shù)： | 27/48頁 |
| 文件大?。?/td> | 378K |
| 代理商： | BU-61582F1-141Q |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
33
Data Device Corporation
www.ddc-web.com
BU-61582
G-08/02-250
ns
0
STRBD high hold time from READYD rising
t18
ns
40
STRBD rising delay to output Data tri-state
t17
ns
0
Output Data hold time following STRBD rising edge
t16
note 6
ns
40
STRBD rising edge delay to IOEN rising edge and READYD rising edge
t15
ns
∞
READYD falling to STRBD rising release time
t14
note 6
ns
0
CLOCK IN rising edge delay to READYD falling
t13
note 2
ns
0
SELECT hold time following IOEN falling
t6
ns
70
Address valid setup time following SELECT and STRBD low (@ 12 MHz)
t4
notes 2, 6
ns
128.3
SELECT and STRBD low delay to IOEN low (uncontended access @ 12 MHz)
t2
ns
10
Address valid setup time prior to CLOCK IN rising edge
t9
note 6
ns
455
437.5
420
IOEN falling delay to READYD falling (reading RAM @ 16 MHz)
t11
note 6
ns
205
187.5
170
IOEN falling delay to READYD falling (reading registers @ 16 MHz)
t11
note 6
ns
600
583.3
565
IOEN falling delay to READYD falling (reading RAM @ 12 MHz)
t11
notes 3, 4, 5
ns
25
MEM/REG, RD/WR hold time prior to CLOCK IN falling edge
t8
note 6
ns
54
Output Data valid prior to READYD falling (@ 12 MHz)
t12
note 6
ns
33
Output Data valid prior to READYD falling (@ 16 MHz)
t12
note 6
ns
265
250
230
IOEN falling delay to READYD falling (reading registers @ 12 MHz)
t11
note 9
ns
25
Address hold time following CLOCK IN rising edge
t10
notes 3, 4, 5
ns
10
MEM/REG, RD/WR setup time prior to CLOCK IN falling edge
t7
ns
30
CLOCK IN rising edge delay to IOEN falling edge
t5
ns
50
Address valid setup time following SELECT and STRBD low (@ 16 MHz)
t4
ns
20
MEM/REG, RD/WR setup time following SELECT and STRBD low(@ 12 MHz)
t3
ns
10
MEM/REG, RD/WR setup time following SELECT and STRBD low(@ 16 MHz)
t3
notes 2, 6
s
5.24
SELECT and STRBD low delay to IOEN low (contended access @ 16 MHz)
t2
notes 2, 6
ns
107.5
SELECT and STRBD low delay to IOEN low (uncontended access @ 16 MHz)
t2
note 2
ns
15
SELECT and STRBD low setup time prior to clock rising edge
t1
NOTE REFERENCE
UNITS
MAX
TYP
MIN
DESCRIPTION
REF
s
6.97
SELECT and STRBD low delay to IOEN low (contended access @ 12 MHz)
t2
TABLE FOR FIGURE 16. CPU READING RAM OR REGISTERS (SHOWN FOR 16-BIT, BUFFERED, NONZERO
WAIT MODE)
Notes for FIGURE 16 and associated table.
1. For the 16-bit buffered configuration, the inputs TRIGGER_SEL
and MSB/LSB may be connected to +5 V or GND. For the nonzero
wait interface ZEROWAIT, must be connected to logic “1”.
2. SELECT and STRBD may be tied together. IOEN goes low on the
first rising CLK edge when SELECT STRBD is sampled low (satis-
fying t2) and the BU-61582’s protocol/memory management logic
is not accessing the internal RAM. When this occurs, IOEN goes
low, starting the transfer cycle. After IOEN goes low, SELECT may
be released high.
3. MEM/REG must be presented high for memory access, low for
register access.
4. MEM/REG and RD/WR are buffered transparently until the first
falling edge of CLK after IOEN goes low. After this CLK edge,
MEM/REG and RD/WR become latched internally.
5. The logic sense for RD/WR in the diagram assumes that POLARI-
TY_SEL is connected to logic "1". If POLARITY_SEL is connected
to logic "0", RD/WR must be asserted low to read.
6. The timing for IOEN, READYD and D15-D0 assumes a 50 pf load.
For loading above 50 pf, the validity of IOEN, READYD, and D15-
D0 is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
7. Timing for A15-A0 assumes ADDR-LAT is connected to logic “1”.
Refer to Address Latch timing for additional details
8. Internal RAM is accessed by A13 through A0. Registers are
accessed by A4 through A0.
9. The address bus A15-A0 is internally buffered transparently until
the first rising edge of CLK after IOEN, goes low. After this CLK
edge, A15-A0 become latched internally.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-61582F1-150Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| BU-61582F2-181 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP70 |
| BU-61582G0-121Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| BU-61582G0-151Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| BU-61582G0-191K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU-61585 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |ACE |
| BU-61586 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |ACE |
| BU61586V6-300 | 制造商:DDC 功能描述:MIL-STD-1553/ARINC BUS CONTROLLER/RTU, 70 Pin, Flat Pack |
| BU-61588 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MINIATURE ADVANCED COMMUNICATION ENGINE (MINI-ACE) AND MINI-ACE PLUS |
| BU-61588F0 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MINIATURE ADVANCED COMMUNICATION ENGINE (MINI-ACE) AND MINI-ACE PLUS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。