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參數(shù)資料
| 型號： | BU-61559F2-660K |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDFP78 |
| 封裝： | 45.70 X 53.30 MM, 5.30 MM HEIGHT, CERAMIC, FP-78 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 438K |
| 代理商： | BU-61559F2-660K |
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21
Data Device Corporation
www.ddc-web.com
BU-61559 Series
E-03/06-0
ADDRESS LATCH TIMING (BUFFERED MODE)
FIGURE 21 illustrates the operation and timing of the address
input latches for the buffered interface mode. In the transparent
mode, the address buffers, and SELECT, MEM/REG inputs are
always transparent (MSB/LSB not applicable). Since the trans-
parent mode requires the use of external buffers, external
address latches would be required to demultiplex a multiplexed
address bus. In the buffered mode however, the BU-61559's
internal address may be used to perform the demultiplexing func-
tion.
FIGURE 21. ADDRESS LATCH TIMING
The operation of the address latches is controlled by means of
the ADDR_LAT input. When ADDR_LAT is high, the latch out-
puts, which drive the BU-61559's internal memory and control
bus, transparently track the state of the address inputs A15
through A00, and the input signals SELECT, MSB/LSB, and
MEM/REG. When ADDR_LAT is low, the internal memory and
control bus remain latched at the state of A15-A00, SELECT,
MSB/LSB, and MEM/REG just prior to the falling edge of
ADDR_LAT.
Notes for FIGURE 21:
1. Applicable to buffered mode only. Address, SELECT, and MEM/REG latches are always transparent in the transparent mode of operation.
2. Latches are transparent when ADDR_LAT is high. Internal values do not update when ADDR_LAT is low.
3. MSB/LSB input signal is applicable to 8-bit mode only (16/8 input = logic "0"). MSB/LSB input is a "don't care" for 16-bit operation.
t3
Propagation delay from external input signals to internal
signals valid
t2
10
ns
10
ns
20
ns
10
ns
MIN
BU-61559
DESCRIPTION
REF
ADDRESS LATCH TIMING
TYP MAX
UNIT
ADDR_LAT high delay to internal signals valid
t1
20
ns
ADDR_LAT pulse width
t4
Input setup time prior to falling edge of ADDR_LAT
t5
Input hold time following falling edge of ADDR_LAT
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