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參數(shù)資料
| 型號： | BTM1A |
| 元件分類： | TVS-瞬態(tài)抑制二極管 |
| 英文描述： | Transient Voltage Suppressor Diodes |
| 中文描述： | 雙差分收發(fā)器 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大小： | 301K |
| 代理商： | BTM1A |
Agere Systems Inc.
13
Data Sheet
October 2001
BTK1A and BTM1A
Dual Differential Transceivers
Latch-Up
Latch-up evaluation has been performed on the data transmission receivers. Latch-up testing determines if the
power-supply current exceeds the specified maximum due to the application of a stress to the device under test. A
device is considered susceptible to latch-up if the power supply current exceeds the maximum level and remains at
that level after the stress is removed.
Agere performs latch-up testing per an internal test method which is consistent with JEDEC Standard No. 17
(previously JC-40.2)
CMOS Latch-Up Standardized Test Procedure
.
Latch-up evaluation involves the following three separate stresses to evaluate latch-up susceptibility levels:
1. dc current stressing of input and output pins.
2. Power supply slew rate.
3. Power supply overvoltage.
Table 10. Latch-Up Test Criteria and Test Results
Based on the results in Table 10, the data transmission receivers pass the Agere latch-up testing requirements and
are considered not susceptible to latch-up.
dc Current Stress
of I/O Pins
≥
150 mA
Power Supply
Slew Rate
≤
1 μs
Power Supply
Overvoltage
≥
1.75 x Vmax
Data Transmission
Receiver ICs
Minimum Criteria
Test Results
≥
250 mA
≤
100 ns
≥
2.25 x Vmax
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