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參數(shù)資料
| 型號： | BT458LPJ135 |
| 英文描述： | Video DAC with Color Palette (RAMDAC) |
| 中文描述： | 視頻DAC的調(diào)色板（的RAMDAC） |
| 文件頁數(shù)： | 14/60頁 |
| 文件大?。?/td> | 647K |
| 代理商： | BT458LPJ135 |
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1.0 Circuit Description
Bt457/Bt458
1.3 MPU Interface
125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC
1-6
Conexant
L45801 Rev. N
1.3 MPU Interface
As illustrated in the functional block diagram on the cover page, the Bt457/458
supports a standard MPU bus interface, allowing the MPU direct access to the
internal control registers and color/overlay palettes. The dual-port color palette
RAM and dual-port overlay registers allow color updating, without contention,
with the display refresh process.
As presented in
Table 1-3
, the C0 and C1 control inputs, in conjunction with
the internal address register, specify which control register, color palette RAM
entry, or overlay register is accessed by the MPU.
The 8-bit address register (ADDR[7:0]) is used to address the internal RAM
and registers, eliminating the requirement for external address multiplexers.
ADDR0 corresponds to D[0] and is the least significant bit.
Bt458 Reading/Writing
Color Data
To write color data, the MPU loads the address register with the address of the
color palette RAM location or overlay register to be modified. The MPU
performs three successive write cycles (red, green, and blue), using C0 and C1 to
select either the color palette RAM or overlay registers. During the blue write
cycle, the three bytes of color information are concatenated into a 24-bit word and
written to the location specified by the address register. The address register then
increments to the next location, which the MPU can modify by writing another
sequence of red, green, and blue data.
To read color data, the MPU loads the address register with the address of the
color palette RAM location or overlay register to be read. The MPU performs
three successive read cycles (red, green, and blue), using C0 and C1 to select
either the color palette RAM or overlay registers. Following the blue read cycle,
the address register increments to the next location, which the MPU can read by
reading another sequence of red, green, and blue data.
Table 1-3. Address Register (ADDR) Operation
ADDR[7:0]
C1
C0
Addressed by MPU
$xx
0
0
Address Register
$00
–
$FF
0
1
Color Palette RAM
$00
1
1
Overlay Color 0
$01
1
1
Overlay Color 1
$02
1
1
Overlay Color 2
$03
1
1
Overlay Color 3
$04
1
0
Read Mask Register
$05
1
0
Blink Mask Register
$06
1
0
Command Register
$07
1
0
Control/Test Register
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相關(guān)代理商/技術(shù)參數(shù) |
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