Bt457/Bt458
2.0 Registers
125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC
2.2 Read Mask Register
L45801 Rev. N
Conexant
2-3
2.2 Read Mask Register
The read mask register enables (logical 1) or disables (logical 0) a bit plane from
addressing the color palette RAM. D[0] corresponds to bit plane 0 (P0 {A
–
E}),
and D[7] corresponds to bit plane 7 (P7 {A
–
E}). Each register bit is logically
ANDed with the corresponding bit plane input. This register can be written to or
read by the MPU at any time and is not initialized. For proper operation, it must
be initialized by the user after power-up.
2.3 Blink Mask Register
The blink mask register enables (logical 1) or disables (logical 0) a bit plane from
blinking at the blink rate and duty cycle specified by the command register. D[0]
corresponds to bit plane 0 (P0 {A
–
E}), and D[7] corresponds to bit plane 7 (P7
{A
–
E}). In order for a bit plane to blink, the corresponding bit in the read mask
register must be a logical 1. This register can be written to or read by the MPU at
any time and is not initialized. For proper operation, it must be initialized by the
user after power-up.
2.4 Bt458 Test Register
The test register provides diagnostic capability by enabling the MPU to read
the D/A converters inputs. It can be written to or read by the MPU at any time and
is not initialized. For proper operation, it must be initialized by the user after
power-up. When writing to the register, the upper 4 bits (D[7:4]) are ignored.
The contents of the test register are defined as follows:
To use the test register, the host MPU writes to it, setting only one of the red,
green, or blue enable bits. These bits specify which four bits of color information
the MPU wishes to read (R[3:0], G[3:0], B[3:0], R[7:4], G[7:4], or B[7:4]). When
the MPU reads the test register, the four bits of color information from the DAC
Table 2-2. Bt458 Test Register
D[7:4]
Color Information
D[3]
Low (Logical 1) or High (Logical 0) Nibble
D[2]
Blue Enable
D[1]
Green Enable
D[0]
Red Enable