參數(shù)資料
型號(hào)： BT457KG125
英文描述： Video DAC with Color Palette (RAMDAC)
中文描述： 視頻DAC的調(diào)色板（的RAMDAC）
文件頁(yè)數(shù)： 16/60頁(yè)
文件大小： 647K
代理商： BT457KG125
1.0 Circuit Description
Bt457/Bt458
1.3 MPU Interface
125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC
1-8
Conexant
L45801 Rev. N
Additional Information
Although the color palette RAM and overlay registers are dual-ported, if the pixel
and overlay data are addressing the same palette entry being written to by the
MPU during the write cycle, one or more of the pixels on the display screen can
be disturbed. A maximum of one pixel is disturbed if the write data from the
MPU is valid during the entire chip enable time.
The control registers are also accessed through the address register in
conjunction with the C0 and C1 inputs, as specified in
Table 1-3
. All control
registers can be written to or read by the MPU at any time. The address register
does not increment following read or write cycles to the control registers,
facilitating read-modify-write operations.
If an invalid address loads into the address register, data written to the device
is ignored, and invalid data is read by the MPU.
Frame Buffer Interface
To enable pixel data to be transferred from the frame buffer at TTL data rates, the
Bt457/458 incorporates internal latches and multiplexers. As illustrated in
Figure 1-3
, on the rising edge of LD*, sync and blank information, color (up to 8
bits per pixel), and overlay (up to 2 bits per pixel) information, for either 4 or 5
consecutive pixels, are latched into the device. With this configuration, the sync
and blank timing is recognized only with 4- or 5-pixel resolution. Typically, the
LD* signal is used to clock external circuitry to generate basic video timing.
Each clock cycle, the Bt457/458 outputs color information based on the {A}
inputs, followed by the {B} inputs, then the {C} inputs, etc., until all 4 or 5 pixels
have been output, at which point the cycle repeats.
The overlay inputs can have pixel timing, facilitating the use of additional bit
planes in the frame buffer to control overlay selection on a pixel basis. On the
other hand, they can be controlled by external character or cursor generation
logic.
To simplify the frame buffer interface timing, LD* can be phase shifted in any
amount relative to CLOCK. This enables the LD* signal to be derived by
externally dividing CLOCK by 4 or 5 independent of the propagation delays of
the LD* generation logic. As a result, the pixel and overlay data are latched on the
rising edge of LD*, independent of the clock phase.
Figure 1-3. Video Input/Output Timing
CLOCK
DATA
IOR, IOG, IOB
(IOUT
–
Bt457)
P[7:0] (A
–
E),
OL[1,0] (A
–
E),
SYNC*, BLANK*
LD*
457-8_014
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