參數(shù)資料
型號: BT457KG110
英文描述: Video DAC with Color Palette (RAMDAC)
中文描述: 視頻DAC的調(diào)色板(的RAMDAC)
文件頁數(shù): 19/60頁
文件大?。?/td> 647K
代理商: BT457KG110
L45801 Rev. N
Conexant
2-1
2
2.0 Registers
2.1 Internal
2.1.1 Command Register
The command register can be written or read by the MPU at any time and is not
initialized. For proper operation, it must be initialized by the user after power-up.
CR0 corresponds to data bus bit D[0].
Table 2-1. Command Registers
(1 of 2)
Function
Description
CR7
Multiplex select
This bit specifies whether 4:1 or 5:1 multiplexing is to be used for the
pixel and overlay inputs. If 4:1 is specified, the {E} pixel and {E} overlay
inputs are ignored and should be connected to GND, and the LD* input
should be one fourth the CLOCK rate. If 5:1 is specified, all of the pixel
and overlay inputs are used, and the LD* input should be one fifth the
CLOCK rate.
The pipeline delay of the Bt457/458 can be reset to a fixed eight clock
cycles. In this instance, each time the input multiplexing is changed, the
Bt457/458 must again be reset to a fixed pipeline delay.
(0)
(1)
4:1 Multiplexing
5:1 Multiplexing
CR6
RAM Enable
When the overlay select bits are 00, this bit specifies whether to use the
color palette RAM or overlay color 0 to provide color information.
(0)
(1)
Use Overlay Color 0
Use Color Palette RAM
CR5,4
Blink Rate Selection
These 2 bits control the blink rate cycle time and duty cycle, and are
specified as the number of vertical retrace intervals. The numbers in
parentheses specify the duty cycle (percent on/off).
(00)
(01)
(10)
(11)
16 on, 48 off (25/75)
16 on, 16 off (50/50)
32 on, 32 off (50/50)
64 on, 64 off (50/50)
CR3
OL1 Blink Enable
If a logical 1, this bit forces the OL1 {A
E} inputs to toggle between a
logical 0 and the input value at the selected blink rate prior to palette
section. A value of logical 0 does not affect the value of the OL1 {A
E}
inputs. In order for overlay 1 bit plane to blink, bit CR1 must be set to a
logical 1.
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