參數(shù)資料
型號: BSP92
廠商: NXP SEMICONDUCTORS
元件分類: 小信號晶體管
英文描述: P-channel enhancement mode vertical D-MOS transistor
中文描述: 180 mA, 240 V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET
封裝: SOT-223, 4 PIN
文件頁數(shù): 2/8頁
文件大小: 52K
代理商: BSP92
April 1995
2
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
BSP92
FEATURES
Low threshold voltage V
GS(th)
Direct interface to C-MOS, TTL,
etc.
High-speed switching
No secondary breakdown.
DESCRIPTION
P-channel enhancement mode
vertical D-MOS transistor in a
SOT223 envelope, intended for use
as a surface-mounted device in line
current interruptor in telephone sets
and for application in relay, high
speed and line transformer drivers.
PINNING - SOT223
PIN
DESCRIPTION
1
2
3
4
gate
drain
source
drain
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
R
DS(on)
V
GS(th)
PARAMETER
MAX.
UNIT
drain-source voltage
DC drain current
drain-source on-resistance
gate-source threshold voltage
240
180
20
1.8
V
mA
V
Fig.1 Simplified outline (SOT223) and symbol.
handbook, halfpage
MAM121
4
1
2
3
Top view
s
d
g
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134).
THERMAL RESISTANCE
Note
1.
Transistor mounted on an epoxy printed circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain tab minimum
6 cm
2
.
SYMBOL
V
DS
±
V
GSO
I
D
I
DM
P
tot
T
stg
T
j
PARAMETER
CONDITIONS
MIN.
65
MAX.
UNIT
drain-source voltage
gate-source voltage
DC drain current
peak drain current
total power dissipation
storage temperature range
junction temperature
240
20
180
720
1.5
150
150
V
V
mA
mA
W
°
C
°
C
open drain
up to T
amb
= 25
°
C (note 1)
SYMBOL
PARAMETER
THERMAL RESISTANCE
R
th j-a
from junction to ambient (note 1)
83.3 K/W
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