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參數(shù)資料
| 型號(hào)： | BS62LV2005TI |
| 廠商： | BRILLIANCE SEMICONDUCTOR, INC. |
| 英文描述： | Very Low Power/Voltage CMOS SRAM 256K X 8 bit |
| 中文描述： | 非常低功率/電壓CMOS SRAM的256K × 8位 |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大?。?/td> | 279K |
| 代理商： | BS62LV2005TI |
R0201-BS62LV2005
Revision 2.4
April 2002
4
R0201-BS62LV2005
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS62LV2005-55
MIN. TYP. MAX.
BS62LV2005-70
MIN. TYP. MAX.
UNIT
t
AVAX
t
RC
Read Cycle Time
55
--
70
--
ns
t
AVQV
t
AA
Address Access Time
--
55
--
70
ns
t
E1LQV
t
ACS1
Chip Select Access Time
(CE1)
--
55
--
70
ns
t
E2HOV
t
ACS2
Chip Select Access Time
(CE2)
--
55
--
70
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
30
--
35
ns
t
E1LQX
t
CLZ1
Chip Select to Output Low Z
(CE1)
10
--
10
--
ns
t
E2HOX
t
CLZ2
Chip Select to Output Low Z
(CE2)
10
--
10
--
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
10
--
10
--
ns
t
E1HQZ
t
CHZ1
Chip Deselect to Output in High Z
(CE1)
0--
30
0
--
35
ns
t
E2HQZ
t
CHZ2
Chip Deselect to Output in High Z
(CE2)
0--
30
0
--
35
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
0--
25
0
--
30
ns
t
AXOX
t
OH
Output Disable to Output Address Change
10
--
10
--
ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 5.0V )
READ CYCLE
AC TEST CONDITIONS
AC TEST LOADS AND WAVEFORMS
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CAR
ANY CHANG
PERMITTED
E:
CHANGE :
E
STATE
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”O(jiān)FF ”STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
BSI
BS62LV2005
667
THEVENIN EQUIVALENT
ALL INPUT PULSES
→
10%
90%
←
Vcc
GND
→
← 5ns
90%
10%
1.73V
OUTPUT
FIGURE 2
5.0V
OUTPUT
INCLUDING
JIG AND
SCOPE
1928
1020
5PF
FIGURE 1B
5.0V
OUTPUT
INCLUDING
JIG AND
SCOPE
1928
100PF
FIGURE 1A
1020
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